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1. 发明授权

US07607048B2 Method and apparatus for protecting TLB's VPN from soft errors 失效
标题翻译：保护TLB VPN免受软错误的方法和设备
公开(公告)号：US07607048B2
公开(公告)日：2009-10-20
申请号：US11026633
申请日：2004-12-30
申请人： Ugonna C. Echeruo , George Z. Chrysos , John H. Crawford , Shubhendu S. Mukherjee
发明人： Ugonna C. Echeruo , George Z. Chrysos , John H. Crawford , Shubhendu S. Mukherjee
IPC分类号： G06F11/00
CPC分类号： G06F12/1027 , G06F2212/1032 , G06F2212/652 , H04L1/0063
摘要： A method and apparatus for protecting a TLB's VPN from soft errors is described. On a TLB lookup, the incoming virtual address is used to CAM the TLB VPN. In parallel with this CAM operation, parity is computed on the incoming virtual address for the possible page sizes supported by the processor. If a matching VPN is found in the TLB, its payload is read out. The encoded page size is used to select which of the set of pre-computed virtual address parity to compare with the stored parity bit in the TLB entry. This has the advantage of removing the computation of parity on the TLB VPN from the critical path of the TLB lookup. Instead it is now in the TLB fill path.
摘要翻译：描述了一种用于保护TLB的VPN免受软错误的方法和装置。在TLB查找中，传入的虚拟地址用于CAM TLB VPN。与该CAM操作并行，对于处理器支持的可能的页面大小，对传入的虚拟地址计算奇偶校验。如果在TLB中找到匹配的VPN，则读出其有效载荷。编码的页面大小用于选择预先计算的虚拟地址奇偶校验中的哪一个与TLB条目中存储的奇偶校验位进行比较。这具有从TLB查找的关键路径去除TLB VPN上的奇偶校验的计算的优点。相反，它现在在TLB填充路径中。

2. 发明授权

US09524009B2 Managing the operation of a computing device by determining performance-power states 有权
标题翻译：通过确定性能 - 功率状态来管理计算设备的操作
公开(公告)号：US09524009B2
公开(公告)日：2016-12-20
申请号：US13976789
申请日：2012-05-14
申请人： Devadatta V. Bodas , John H. Crawford
发明人： Devadatta V. Bodas , John H. Crawford
IPC分类号： G06F1/00 , G06F11/30 , G06F1/32 , G06F1/26 , G06F9/50
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/3203 , G06F9/5094 , Y02D10/22
摘要： A method and system for managing the operation of a computing system are described herein. The method includes determining a number of workloads on the computing system. The method also includes determining a number of performance-power states for each workload and a corresponding performance range and power consumption range for each performance-power state. The method further includes managing performance and power consumption of the computing system based on the performance-power states.
摘要翻译：本文描述了用于管理计算系统的操作的方法和系统。该方法包括确定计算系统上的多个工作负载。该方法还包括为每个工作负载确定多个性能功率状态，以及为每个性能功率状态确定相应的性能范围和功耗范围。该方法还包括基于性能 - 功率状态管理计算系统的性能和功耗。

3. 发明申请

US20140310550A1 PCIE DEVICE POWER STATE CONTROL 有权
标题翻译： PCIE设备电源状态控制
公开(公告)号：US20140310550A1
公开(公告)日：2014-10-16
申请号：US13976545
申请日：2011-12-30
申请人： Anil K. Kumar , John H. Crawford , Paul S. Diefenbaugh
发明人： Anil K. Kumar , John H. Crawford , Paul S. Diefenbaugh
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/3203 , G06F1/3215 , G06F1/3234 , G06F1/325 , G06F11/3051
摘要： An apparatus, system, and method, the method including receiving an indication of a idle state capability of a platform connected device; determining, by a chipset, an idle power state compatible with the device; and directing the device to enter the determined idle power state based on a power state of the chipset.
摘要翻译：一种装置，系统和方法，所述方法包括：接收平台连接设备的空闲状态能力的指示; 通过芯片组确定与所述设备兼容的空闲功率状态; 以及基于所述芯片组的功率状态来指示所述设备进入所确定的空闲功率状态。

4. 发明申请

US20110252203A1 TRANSACTION BASED SHARED DATA OPERATIONS IN A MULTIPROCESSOR ENVIRONMENT 有权
公开(公告)号：US20110252203A1
公开(公告)日：2011-10-13
申请号：US13168171
申请日：2011-06-24
申请人： Sailesh Kottapalli , John H. Crawford , Kushagra Vaid
发明人： Sailesh Kottapalli , John H. Crawford , Kushagra Vaid
IPC分类号： G06F12/08
CPC分类号： G06F9/528 , G06F9/3834 , G06F9/544
摘要： The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

5. 发明申请

US20110173634A1 Synchronizing Multiple Threads Efficiently 有权
标题翻译：高效同步多线程
公开(公告)号：US20110173634A1
公开(公告)日：2011-07-14
申请号：US13069684
申请日：2011-03-23
申请人： Sailesh Kottapalli , John H. Crawford
发明人： Sailesh Kottapalli , John H. Crawford
IPC分类号： G06F9/46
CPC分类号： G06F9/522 , G06F9/52 , G06F12/084 , G06F12/0842 , G06F12/0857
摘要： In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括为多个线程中的每个线程分配共享变量内的位置并将值写入相应位置以指示相应线程已经达到屏障的方法。以这种方式，当所有线程都到达障碍物时，建立同步。在一些实施例中，共享变量可以存储在可由多个线程访问的高速缓存中。描述和要求保护其他实施例。

6. 发明申请

US20080163014A1 TRACKING HEALTH OF INTEGRATED CIRCUIT STRUCTURES 有权
标题翻译：跟踪整体电路结构的健康状况
公开(公告)号：US20080163014A1
公开(公告)日：2008-07-03
申请号：US11618766
申请日：2006-12-30
申请人： John H. Crawford , Tsvika Kurts , Moty Mehalel
发明人： John H. Crawford , Tsvika Kurts , Moty Mehalel
IPC分类号： G11C29/00
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： Methods and apparatus to track the health of integrated circuit structures are described. In an embodiment, a counter may be updated when the status of a portion of a storage unit (e.g., a cache) transitions to a defective status (e.g., as determined by reference to one or more corresponding status bits). The value stored in the counter may be compared with a threshold value, e.g., to generate a signal that is indicative of whether the threshold value has been exceeded. Other embodiments are also described.
摘要翻译：描述了跟踪集成电路结构健康的方法和装置。在一个实施例中，当存储单元（例如，高速缓存）的一部分的状态转变到缺陷状态（例如，通过参考一个或多个相应的状态位确定）时，可以更新计数器。存储在计数器中的值可以与阈值进行比较，例如，以产生指示阈值是否已被超过的信号。还描述了其它实施例。

7. 发明授权

US5131083A Method of transferring burst data in a microprocessor 失效
标题翻译：在微处理器中传输脉冲数据的方法
公开(公告)号：US5131083A
公开(公告)日：1992-07-14
申请号：US333980
申请日：1989-04-05
申请人： John H. Crawford , Edward T. Grochowski
发明人： John H. Crawford , Edward T. Grochowski
IPC分类号： G06F13/16 , G06F12/02 , G06F12/04 , G06F12/08 , G06F13/28
CPC分类号： G06F12/0879 , G06F13/28
摘要： An improved method of transferring burst data in a microprocessor is described. The improvement lies in the burst ordering of the data items to be referenced. The original address is selected as the data item that the user initially wants to access. Subsequent addresses in the burst are generated according to a mathematical algorithm. The algorithm generates the remaining addresses as a function of the internal bus width, the external memory/bus line size and the original address. Using the burst sequence of the present invention, memories/buses of different widths can be smoothly coupled to a microprocessor having a fixed CPU bus size (e.g., 32 bits).
摘要翻译：描述了一种在微处理器中传送突发数据的改进方法。改进在于要引用的数据项的突发排序。原始地址被选择为用户最初要访问的数据项。突发中的后续地址根据数学算法生成。该算法根据内部总线宽度，外部存储器/总线大小和原始地址生成剩余的地址。使用本发明的脉冲序列，可以将具有不同宽度的存储器/总线平滑地耦合到具有固定CPU总线大小（例如，32位）的微处理器。

8. 发明授权

US4240785A Wood burner 失效
标题翻译：木材燃烧器
公开(公告)号：US4240785A
公开(公告)日：1980-12-23
申请号：US17431
申请日：1979-03-05
申请人： John H. Crawford
发明人： John H. Crawford
IPC分类号： F23G5/32 , F23G7/10 , F23M5/08 , F26B23/02 , F23D15/02
CPC分类号： F23G5/32 , F23G7/105 , F23M5/085 , F26B23/028
摘要： Apparatus for burning combustible particles to heat circulated air. The apparatus includes an upright housing containing a removable liner which forms the combustion chamber of the burner, and a perforated, intermediate wall member which forms, with the walls of the housing and the liner, outer and inner gas-receiving spaces, respectively. Air injected into the housing passes from the outer, into the inner gas-receiving space, where the gas is directed, through tuyeres in the liner, into the chamber, substantially tangentially to the wall thereof, producing a gas vortex therein. Particles introduced into the chamber through an upper opening are combusted primarily in the chamber's upper core region with such combustion being supported by, and acting to heat, vortexing gas within the chamber prior to its discharge through a lower chamber opening.
摘要翻译：用于燃烧可燃颗粒以加热循环空气的装置。该装置包括容纳可形成燃烧器的燃烧室的可拆卸衬套的直立壳体，以及分别与壳体和衬套的壁分别形成外部和内部气体接收空间的穿孔的中间壁构件。注入壳体的空气从内部通过气体导向的内部气体接收空间，通过衬套中的风嘴进入到与其壁基本切线的腔室中，在其中产生气体涡流。通过上部开口引入到腔室中的颗粒主要在腔室的上部核心区域中燃烧，这种燃烧在腔室内通过下部腔室开口排出之前由腔室中的涡流气体支撑并起到加热作用。

9. 发明申请

US20150089183A1 MAPPING A PHYSICAL ADDRESS DIFFERENTLY TO DIFFERENT MEMORY DEVICES IN A GROUP 有权
标题翻译：映射一个物理地址不同于一组中的不同的存储器件
公开(公告)号：US20150089183A1
公开(公告)日：2015-03-26
申请号：US14038659
申请日：2013-09-26
申请人： KULJIT S. BAINS , Suneeta Sah , John H. Crawford , Brian S. Morris
发明人： KULJIT S. BAINS , Suneeta Sah , John H. Crawford , Brian S. Morris
IPC分类号： G06F12/06
CPC分类号： G06F12/06 , G06F12/0292 , G06F12/0638
摘要： A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device.
摘要翻译：存储器子系统包括连接到地址总线的一组存储器件。存储器子系统包括将存储器访问命令的物理地址唯一地映射到组的每个存储器件的逻辑。因此，由相关联的存储器控制器发送的每个物理地址唯一地访问每个存储器件的不同行，而不是映射到每个存储器件的相同或对应的行。

10. 发明申请

US20140281207A1 Techniques for Determining Victim Row Addresses in a Volatile Memory 有权
标题翻译：用于确定易失性存储器中的受害者行地址的技术
公开(公告)号：US20140281207A1
公开(公告)日：2014-09-18
申请号：US14133011
申请日：2013-12-18
申请人： Sreenivas Mandava , Brian S. Morris , Suneeta Sah , Roy M. Stevens , Ted Rossin , Mathew W. Stefaniw , John H. Crawford
发明人： Sreenivas Mandava , Brian S. Morris , Suneeta Sah , Roy M. Stevens , Ted Rossin , Mathew W. Stefaniw , John H. Crawford
IPC分类号： G11C11/406 , G11C14/00
CPC分类号： G11C14/0009 , G06F12/10 , G06F2212/1032 , G11C7/02 , G11C11/406
摘要： Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
摘要翻译：公开了用于基于侵入者行的逻辑地址和与易失性存储器相关联的地址转换方案来确定易失性存储器的一个或多个受害行的逻辑地址的示例。其他的例子被描述和要求保护。

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