专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150089183A1 MAPPING A PHYSICAL ADDRESS DIFFERENTLY TO DIFFERENT MEMORY DEVICES IN A GROUP 有权
标题翻译：映射一个物理地址不同于一组中的不同的存储器件
公开(公告)号：US20150089183A1
公开(公告)日：2015-03-26
申请号：US14038659
申请日：2013-09-26
申请人： KULJIT S. BAINS , Suneeta Sah , John H. Crawford , Brian S. Morris
发明人： KULJIT S. BAINS , Suneeta Sah , John H. Crawford , Brian S. Morris
IPC分类号： G06F12/06
CPC分类号： G06F12/06 , G06F12/0292 , G06F12/0638
摘要： A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device.
摘要翻译：存储器子系统包括连接到地址总线的一组存储器件。存储器子系统包括将存储器访问命令的物理地址唯一地映射到组的每个存储器件的逻辑。因此，由相关联的存储器控制器发送的每个物理地址唯一地访问每个存储器件的不同行，而不是映射到每个存储器件的相同或对应的行。

2. 发明申请

US20140281207A1 Techniques for Determining Victim Row Addresses in a Volatile Memory 有权
标题翻译：用于确定易失性存储器中的受害者行地址的技术
公开(公告)号：US20140281207A1
公开(公告)日：2014-09-18
申请号：US14133011
申请日：2013-12-18
申请人： Sreenivas Mandava , Brian S. Morris , Suneeta Sah , Roy M. Stevens , Ted Rossin , Mathew W. Stefaniw , John H. Crawford
发明人： Sreenivas Mandava , Brian S. Morris , Suneeta Sah , Roy M. Stevens , Ted Rossin , Mathew W. Stefaniw , John H. Crawford
IPC分类号： G11C11/406 , G11C14/00
CPC分类号： G11C14/0009 , G06F12/10 , G06F2212/1032 , G11C7/02 , G11C11/406
摘要： Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
摘要翻译：公开了用于基于侵入者行的逻辑地址和与易失性存储器相关联的地址转换方案来确定易失性存储器的一个或多个受害行的逻辑地址的示例。其他的例子被描述和要求保护。

3. 发明授权

US09442871B2 Accessing data stored in a command/address register device 有权
标题翻译：访问存储在命令/地址寄存器中的数据
公开(公告)号：US09442871B2
公开(公告)日：2016-09-13
申请号：US13995477
申请日：2011-12-22
申请人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
发明人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
IPC分类号： G06F13/28 , G06F11/10 , G06F11/16 , G11C29/44 , G06F13/16
CPC分类号： G11C7/1072 , G06F11/073 , G06F11/0787 , G06F11/10 , G06F11/1004 , G06F11/1016 , G06F11/1612 , G06F13/16 , G06F13/28 , G11C7/1006 , G11C29/44 , G11C2029/0411 , G11C2029/4402
摘要： A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.
摘要翻译：通过将地址总线上的数据传送到连接到数据总线的设备，可以读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。然后主机处理器从存储器件的寄存器读取信息。

4. 发明申请

US20140089576A1 METHOD, APPARATUS AND SYSTEM FOR PROVIDING A MEMORY REFRESH 有权
标题翻译：方法，提供记忆刷新的装置和系统
公开(公告)号：US20140089576A1
公开(公告)日：2014-03-27
申请号：US13625741
申请日：2012-09-24
申请人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
发明人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
IPC分类号： G06F12/00
CPC分类号： G11C16/00 , G06F13/1636 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.
摘要翻译：一个内存控制器，用于实现行锤事件潜在的受害者行的目标刷新。在一个实施例中，存储器控制器接收指示存储器设备的特定行正经历重复访问，这威胁到与特定行物理相邻的一个或多个受害者行中的数据的完整性。存储器控制器在没有指定存储器件的物理相邻行之间的偏移的地址映射信息的情况下访问默认偏移信息。在另一个实施例中，存储器控制器基于默认偏移信息来确定潜在的受害者行的地址。响应于所接收到的行锤事件的指示，存储器控制器向确定的多个地址中的每一个发送相应的命令给存储器设备，其中命令用于存储设备执行目标刷新潜在的受害者行。

5. 发明授权

US09030903B2 Method, apparatus and system for providing a memory refresh 有权
标题翻译：用于提供存储器刷新的方法，装置和系统
公开(公告)号：US09030903B2
公开(公告)日：2015-05-12
申请号：US13625741
申请日：2012-09-24
申请人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
发明人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
IPC分类号： G11C11/406 , G11C16/00 , G06F13/16
CPC分类号： G11C16/00 , G06F13/1636 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.
摘要翻译：一个内存控制器，用于实现行锤事件潜在的受害者行的目标刷新。在一个实施例中，存储器控制器接收指示存储器设备的特定行正经历重复访问，这威胁到与特定行物理相邻的一个或多个受害者行中的数据的完整性。存储器控制器在没有指定存储器件的物理相邻行之间的偏移的地址映射信息的情况下访问默认偏移信息。在另一个实施例中，存储器控制器基于默认偏移信息来确定潜在的受害者行的地址。响应于所接收到的行锤事件的指示，存储器控制器向确定的多个地址中的每一个发送相应的命令给存储器设备，其中命令用于存储设备执行目标刷新潜在的受害者行。

6. 发明申请

US20140372816A1 ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE 有权
标题翻译：访问存储在命令/地址寄存器设备中的数据
公开(公告)号：US20140372816A1
公开(公告)日：2014-12-18
申请号：US13995477
申请日：2011-12-22
申请人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
发明人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
IPC分类号： G06F11/10 , G06F11/16 , G11C29/44
CPC分类号： G11C7/1072 , G06F11/073 , G06F11/0787 , G06F11/10 , G06F11/1004 , G06F11/1016 , G06F11/1612 , G06F13/16 , G06F13/28 , G11C7/1006 , G11C29/44 , G11C2029/0411 , G11C2029/4402
摘要： A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.
摘要翻译：通过将地址总线上的数据传送到连接到数据总线的设备，可以读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。然后主机处理器从存储器件的寄存器读取信息。

7. 发明申请

US20140244922A1 MULTI-PURPOSE REGISTER PROGRAMMING VIA PER DRAM ADDRESSABILITY MODE 审中-公开
标题翻译：多目标寄存器通过DRAM可寻址模式编程
公开(公告)号：US20140244922A1
公开(公告)日：2014-08-28
申请号：US13997911
申请日：2012-01-20
申请人： Kuljit S. Bains , Suneeta Sah
发明人： Kuljit S. Bains , Suneeta Sah
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G11C11/4076
摘要： Embodiments of an apparatus, system and method for using Per DRAM Addressability (PDA) to program Multi-Purpose Registers (MPRs) of a dynamic random access memory (DRAM) device are described herein. Embodiments of the invention allow unique 32 bit patterns to be stored for each DRAM device on a rank, thereby enabling data bus training to be done in parallel. Furthermore, embodiments of the invention provide 32 bits of storage per DRAM device on a rank for the system BIOS for storing codes such as MR values, or for any other purpose (e.g., temporary scratch storage to be used by BIOS processes).
摘要翻译：本文描述了使用每DRAM可寻址性（PDA）来编程动态随机存取存储器（DRAM）设备的多用途寄存器（MPR）的装置，系统和方法的实施例。本发明的实施例允许为等级上的每个DRAM设备存储唯一的32位模式，从而使数据总线训练能够并行完成。此外，本发明的实施例在用于存储诸如MR值的代码或用于任何其他目的（例如，由BIOS处理使用的临时临时存储）的系统BIOS的等级上为每个DRAM设备提供32位存储。

8. 发明申请

US20140192605A1 MEMORY REFRESH MANAGEMENT 有权
标题翻译：记忆刷新管理
公开(公告)号：US20140192605A1
公开(公告)日：2014-07-10
申请号：US13761385
申请日：2013-02-07
申请人： John H. Crawford , Suneeta Sah
发明人： John H. Crawford , Suneeta Sah
IPC分类号： G11C7/00
CPC分类号： G06F3/0613 , G06F3/0658 , G06F3/0659 , G06F3/0673 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/4076
摘要： Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency. Other embodiments are also disclosed and claimed.
摘要翻译：描述了管理存储器刷新操作的装置，系统和方法。在一个实施例中，电子设备包括处理器和存储器控制器逻辑，用于确定存储器系统的存储器刷新频率，并且根据存储器刷新频率向连接到存储器控制器的至少一个存储器组中的刷新控制逻辑发送刷新命令。还公开并要求保护其他实施例。

9. 发明授权

US08122265B2 Power management using adaptive thermal throttling 有权
标题翻译：电源管理采用自适应热调节
公开(公告)号：US08122265B2
公开(公告)日：2012-02-21
申请号：US11648253
申请日：2006-12-29
申请人： Sivakumar Radhakrishnan , Suneeta Sah , William H. Nale , Rami Naqib , Howard S. David , Rajat Agarwal
发明人： Sivakumar Radhakrishnan , Suneeta Sah , William H. Nale , Rami Naqib , Howard S. David , Rajat Agarwal
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203
摘要： In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.
摘要翻译：在一些实施例中，芯片包括调度器，发射机，接收机和控制电路。时间表调度要在芯片外部发送的信号，并且发送器在芯片外发送调度信号。接收器接收包括具有与芯片外的温度有关的温度信息的信号的信号。控制电路选择性地限制可以在一系列较小窗口内调度的多个命令，同时检查靠近包括许多较小窗口的较大窗口的结论的温度信息。描述其他实施例。

10. 发明申请

US20140281805A1 SELECTIVE REMEDIAL ACTION BASED ON CATEGORY OF DETECTED ERROR FOR A MEMORY READ 有权
标题翻译：基于存储器读取的检测错误类别的选择性补救措施
公开(公告)号：US20140281805A1
公开(公告)日：2014-09-18
申请号：US13797681
申请日：2013-03-12
申请人： Suneeta Sah
发明人： Suneeta Sah
IPC分类号： G06F11/08
CPC分类号： G06F11/1048 , G06F11/1004 , G11C29/42
摘要： Embodiments of apparatus, methods, systems, computer-readable storage media and devices are described herein for determining an error category for a detected error in data read from a volatile memory; and selectively performing or causing an additional remedial action based at least in part on the error category determined. In various embodiments, the determining and the performing or causing may be undertaken in response to the correcting. The memory may be volatile or non-volatile memory. Other embodiments may be described and/or claimed.
摘要翻译：本文描述了装置，方法，系统，计算机可读存储介质和设备的实施例，用于确定从易失性存储器读取的数据中检测到的错误的错误类别; 以及至少部分地基于所确定的错误类别选择性地执行或引起额外的补救措施。在各种实施例中，可以响应于校正而进行确定和执行或导致。存储器可能是易失性或非易失性存储器。可以描述和/或要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式