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1. 发明授权

US5268317A Method of forming shallow junctions in field effect transistors 失效
标题翻译：在场效应晶体管中形成浅结的方法
公开(公告)号：US5268317A
公开(公告)日：1993-12-07
申请号：US790953
申请日：1991-11-12
申请人： Udo Schwalke , Christoph Zeller , Heinrich J. Zeininger , Wilfried Hansch
发明人： Udo Schwalke , Christoph Zeller , Heinrich J. Zeininger , Wilfried Hansch
IPC分类号： H01L29/78 , H01L21/225 , H01L21/265 , H01L21/336 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/2257 , H01L21/2652 , H01L29/41783
摘要： A method of making a MOS field effect transistor having shallow source and drain regions with improved breakdown and leakage characteristics includes the step of forming a layer of a metal silicide along a surface of a body of silicon at each side of a gate which is on an insulated from the surface. A high concentration of an impurity of a desired conductivity type is implanted only into the metal silicide layers. A lower concentration of the impurity is then implanted through the metal silicide layers and into the body just beneath the metal silicide layers. The body is then annealed at a temperature which drives the impurities from the metal silicide layer into the body to form the junctions.

2. 发明授权

US5602410A Off-state gate-oxide field reduction in CMOS 失效
标题翻译： CMOS中的非状态栅氧化物场减少
公开(公告)号：US5602410A
公开(公告)日：1997-02-11
申请号：US519669
申请日：1995-08-25
申请人： Udo Schwalke , Wilfried Hansch
发明人： Udo Schwalke , Wilfried Hansch
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/823842 , H01L29/4916
摘要： A MOSFET device utilizes the gate depletion effect to reduce the oxide field over the junction area. Since the gate depletion effect is present in the non-conducting off state for n.sup.+ gate PMOS devices and p.sup.+ gate NMOS devices, performance degradation is overcome. The level of doping of the gate is critical. In order to prevent gate depletion in the conducting, on state, the NMOS FET must use a highly doped n.sup.+ gate. The PMOS FET n.sup.+ gate must be non-degeneratively doped in order to utilize the advantage of the gate depletion in the non-conducting, off state. This is accomplished by implanting different doses of the same dopant type into the different gates. The MOSFET device can be implemented equally well for n.sup.+ gate PMOS FET devices as well as for p.sup.+ gate NMOS FET devices.
摘要翻译： MOSFET器件利用栅极耗尽效应来减少接合区域上的氧化物场。由于栅极耗尽效应存在于n +栅极PMOS器件和p +栅极NMOS器件的非导通截止状态，因此克服了性能下降。栅极的掺杂水平至关重要。为了防止导通，导通状态下的栅极耗尽，NMOS FET必须使用高掺杂n +栅极。 PMOS FET n +栅极必须是非退化掺杂的，以便利用非导通关断状态下栅极耗尽的优点。这是通过将不同剂量的相同掺杂剂类型注入不同的栅极来实现的。对于n +栅极PMOS FET器件以及p +栅极NMOS FET器件，可以均匀地实现MOSFET器件。

3. 发明授权

US5780929A Formation of silicided junctions in deep submicron MOSFETS by defect enhanced CoSi2 formation 失效
标题翻译：通过缺陷增强CoSi2形成在深亚微米MOSFET中形成硅化物结
公开(公告)号：US5780929A
公开(公告)日：1998-07-14
申请号：US744132
申请日：1996-11-05
申请人： Heinrich Zeininger , Christoph Zeller , Udo Schwalke , Uwe Doebler , Wilfried Haensch
发明人： Heinrich Zeininger , Christoph Zeller , Udo Schwalke , Uwe Doebler , Wilfried Haensch
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L29/45 , H01L29/78 , H01L23/532 , H01L29/43
CPC分类号： H01L29/456 , H01L21/28518 , H01L2924/0002 , Y10S148/017 , Y10S148/019 , Y10S438/974
摘要： Deep submicran mosfets with defect enhanced CoSi2 formation and improved silicided junctions. A silicon wafer having a diffusion window is first precleaned with hydrofluoric acid. After the HF precleaning, the silicon wafer is transferred to a conventional cobalt sputtering tool where it is sputter cleaned by bombardment with low energy Ar+ions so as to form an ultra-shallow damage region. After the sputter cleaning, and without removing the wafer from the sputtering tool, Cobalt metal is deposited on the silicon wafer at room temperature and a CoSi2 layer is formed in the diffusion window.
摘要翻译：具有缺陷增强的CoSi 2形成和改进的硅化物结的深亚微米硅。具有扩散窗的硅晶片首先用氢氟酸预清洗。在HF预清洗之后，将硅晶片转移到常规的钴溅射工具，其中通过用低能Ar +离子轰击进行溅射清洗，以形成超浅损伤区域。在溅射清洗之后，并且不从溅射工具移除晶片，在室温下将钴金属沉积在硅晶片上，并且在扩散窗中形成CoSi 2层。

4. 发明授权

US5344793A Formation of silicided junctions in deep sub-micron MOSFETs by defect enhanced CoSi2 formation 失效
标题翻译：通过缺陷增强CoSi2形成在深亚微米MOSFET中形成硅化物结
公开(公告)号：US5344793A
公开(公告)日：1994-09-06
申请号：US26944
申请日：1993-03-05
申请人： Heinrich Zeininger , Christoph Zeller , Udo Schwalke , Uwe Doebler , Wilfried Haensch
发明人： Heinrich Zeininger , Christoph Zeller , Udo Schwalke , Uwe Doebler , Wilfried Haensch
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L29/45 , H01L29/78 , H01L21/283 , H01L21/302
CPC分类号： H01L29/456 , H01L21/28518 , H01L2924/0002 , Y10S148/017 , Y10S148/019 , Y10S438/974
摘要： An method of providing defect enhanced CoSi2 formation and improved silicided junctions in deep submicron MOSFETs. A silicon wafer having a diffusion window is first precleaned with hydrofluoric acid. After the HF precleaning, the silicon wafer is transferred to a conventional cobalt sputtering tool where it is sputter cleaned by bombardment with low energy Ar+ ions so as to form an ultra-shallow damage region. After the sputter cleaning, and without removing the wafer from the sputtering tool, Cobalt metal is deposited on the silicon wafer at room temperature and a CoSi2 layer is formed in the diffusion window.
摘要翻译：在深亚微米MOSFET中提供缺陷增强的CoSi2形成和改进的硅化物结的方法。具有扩散窗的硅晶片首先用氢氟酸预清洗。在HF预清洗之后，将硅晶片转移到常规的钴溅射工具，其中通过用低能Ar +离子轰击进行溅射清洗，以形成超浅损伤区域。在溅射清洗之后，并且不从溅射工具移除晶片，在室温下将钴金属沉积在硅晶片上，并且在扩散窗中形成CoSi 2层。

5. 发明授权

US5965926A Circuit structure having at least one MOS transistor and method for its production 失效
标题翻译：具有至少一个MOS晶体管的电路结构及其制造方法
公开(公告)号：US5965926A
公开(公告)日：1999-10-12
申请号：US829939
申请日：1997-04-01
申请人： Udo Schwalke
发明人： Udo Schwalke
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/76 , H01L29/94
CPC分类号： H01L29/4983 , H01L21/823842 , H01L27/0928
摘要： A circuit structure having at least one MOS transistor whose source/drain regions are doped by a first conductivity type and whose gate electrode is doped by a conductivity type which is opposite to the first. The gate electrode has a lower dopant concentration at at least one of its edges than in its center. In the ON state, the gate electrode is driven to accumulation, with the result being that no gate depletion occurs. Such a circuit structure is also suitable for CMOS circuits containing PMOS transistors having an n-doped gate.
摘要翻译：具有至少一个MOS晶体管的电路结构，其源极/漏极区域被第一导电类型掺杂，并且其栅极掺杂有与第一导电类型相反的导电类型。栅电极在其边缘中的至少一个边缘处的掺杂剂浓度低于其中心。在导通状态下，驱动栅电极进行累积，结果是不会发生栅耗尽。这种电路结构也适用于含有具有n掺杂栅极的PMOS晶体管的CMOS电路。

6. 发明授权

US5473181A Integrated circuit arrangement having at least one power component and low-voltage components 失效
标题翻译：具有至少一个功率分量和低电压分量的集成电路装置
公开(公告)号：US5473181A
公开(公告)日：1995-12-05
申请号：US314710
申请日：1994-09-29
申请人： Udo Schwalke , Michael Stoisiek
发明人： Udo Schwalke , Michael Stoisiek
IPC分类号： H01L21/8249 , H01L27/06 , H01L29/78 , H01L27/00 , H01L23/544
CPC分类号： H01L27/0688 , H01L29/7802 , H01L2924/0002
摘要： In an integrated circuit arrangement having at least one power component and low-voltage components, the at least one power component is realized in a semiconductor substrate. At least one contact of the power component is arranged on a principal surface of the substrate. The contact is covered with an insulation layer at a surface of which at least one thin-film component, particularly a thin-film transistor, is provided above the contact.
摘要翻译：在具有至少一个功率分量和低电压分量的集成电路装置中，在半导体衬底中实现该至少一个功率分量。功率元件的至少一个触点设置在基板的主表面上。触点被绝缘层覆盖，其表面上至少有一个薄膜部件，特别是薄膜晶体管被提供在触头上方。

7. 发明授权

US06380015B1 MOSFETs with improved short channel effects and method of making the same 有权
标题翻译：具有改善短沟道效应的MOSFET及其制作方法
公开(公告)号：US06380015B1
公开(公告)日：2002-04-30
申请号：US09306617
申请日：1999-05-06
申请人： Udo Schwalke
发明人： Udo Schwalke
IPC分类号： H01L218238
CPC分类号： H01L29/4916 , H01L21/823842 , H01L27/0922 , H01L27/0928 , H01L29/4933
摘要： In the manufacture of CMOS devices, the n+ gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and gate oxide fields for improved reliability. A doped polysilicon layer is formed over a silicon or silicon oxide substrate, and is counterdoped with boron to a level of about 1×1013/cm2 to 5×1016/cm2 to adjust the work function but without changing the essentially n-type character of the gate electrode. This single counterdoping step achieves improved results for sub-micron devices below 0.5 micron at low cost. For CMOS device manufacturing, the alternating n-type and p-type devices are made in similar manner but reversing the n-type and p-type dopants.
摘要翻译：在CMOS器件的制造中，n +栅极部分地与硼反向以产生改进的p型FET，其具有改善的短沟道效应，减小的栅极感应漏极泄漏和栅极氧化物场以提高可靠性。掺杂的多晶硅层形成在硅或氧化硅衬底上，并且与硼相反，达到约1×10 13 / cm 2至5×10 16 / cm 2的水平以调节功函数，但不改变栅电极的基本n型特性。这种单一的反掺杂步骤以低成本实现了低于0.5微米的亚微米器件的改进结果。对于CMOS器件制造，交替的n型和p型器件以类似的方式制造，但是颠倒了n型和p型掺杂剂。

8. 发明授权

US6057211A Method for manufacturing an integrated circuit arrangement 失效
标题翻译：集成电路装置的制造方法
公开(公告)号：US6057211A
公开(公告)日：2000-05-02
申请号：US990516
申请日：1997-12-15
申请人： Udo Schwalke
发明人： Udo Schwalke
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76229
摘要： In a method for manufacturing an integrated circuit arrangement, trenches that define active zones are formed in a substrate. A first insulating layer that fills the narrow trenches is conformally deposited and is structured with a mask and anisotropic etching such that spacers arise at sidewalls of the wide trenches and supporting locations arise in a region of the wide trenches. The surface of the active zones is uncovered by forming a second insulating layer with an essentially planar surface and by a planarizing layer erosion on the basis of chemical-mechanical polishing or conventional dry etching.
摘要翻译：在用于制造集成电路装置的方法中，限定有源区的沟槽形成在衬底中。填充窄沟槽的第一绝缘层被共形沉积，并且用掩模和各向异性蚀刻构造，使得间隔物出现在宽沟槽的侧壁处，并且支撑位置出现在宽沟槽的区域中。通过形成具有基本上平坦的表面的第二绝缘层和基于化学机械抛光或常规干法蚀刻的平坦化层侵蚀来覆盖活性区的表面。

9. 发明授权

US5882964A Process for the production of an integrated CMOS circuit 失效
标题翻译：用于生产集成CMOS电路的工艺
公开(公告)号：US5882964A
公开(公告)日：1999-03-16
申请号：US719411
申请日：1996-09-24
申请人： Udo Schwalke
发明人： Udo Schwalke
IPC分类号： H01L21/265 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L21/823842 , H01L27/0928
摘要： In order to produce an integrated CMOS circuit, a dielectric layer and a silicon layer are applied to a substrate. During the formation of insulation structurers which insulate neighboring active regions in the substrate, the silicon layer is structured in such a way that it has separate sub-regions which are subsequently doped differently. By full-surface deposition of an electrically conductive layer and common structuring of the electrically conductive layer and the structured silicon layer differently doped gate electrodes and a metallization plane, by which the gate electrodes are electrically connected, are formed. Division of the silicon layer before doping prevents lateral dopant diffusion.
摘要翻译：为了制造集成的CMOS电路，将介电层和硅层施加到基板。在绝缘结构体的形成期间，绝缘结构体绝缘在衬底中的相邻有源区，硅层以这样一种方式构造，使得其具有不同的不同掺杂的子区。通过导电层的全表面沉积以及导电层和结构化硅层的不同掺杂栅电极和栅极电连接的金属化平面的共同构造。掺杂前的硅层划分可防止横向掺杂剂扩散。

10. 发明授权

US5872382A Low junction leakage mosfets with particular sidewall spacer structure 失效
标题翻译：具有特殊侧壁间隔结构的低结漏电MOSFET
公开(公告)号：US5872382A
公开(公告)日：1999-02-16
申请号：US908125
申请日：1997-08-11
申请人： Udo Schwalke , Heinz Zeininger
发明人： Udo Schwalke , Heinz Zeininger
IPC分类号： H01L21/225 , H01L21/265 , H01L21/336 , H01L21/338 , H01L21/8238 , H01L29/78 , H01L29/812 , H01L29/76 , H01L27/088 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/2257 , H01L21/2652 , H01L21/823814 , H01L29/41783 , H01L29/7833 , Y10S257/90
摘要： Shallow junction field effect transistors are made by a low temperature process comprising ion implanting source/drain regions through a buffer layer in two steps, the first an ion implant at high dosage and low energy and the second an ion implant at low dosage and high energy. Ion implantation through the buffer layer avoids crystallographic damage to the silicon substrate. By grading the sidewall spacers of the gate electrode, more or fewer ions can be implanted through the spacer foot to ensure continuity between the source/drain regions and the channel region under the gate electrode.
摘要翻译：浅结场效应晶体管由低温工艺制成，包括通过两个步骤的缓冲层的离子注入源极/漏极区域，第一个以高剂量和低能量的离子注入，第二个是低剂量和高能量的离子注入。通过缓冲层的离子注入避免了对硅衬底的晶体损伤。通过对栅电极的侧壁间隔进行分级，可以通过间隔脚注入更多或更少的离子，以确保源/漏区与栅电极下方的沟道区之间的连续性。

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