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1. 发明申请

US20080100340A1 Low voltage complementary metal oxide semiconductor process tri-state buffer 有权
标题翻译：低电压互补金属氧化物半导体工艺三态缓冲器
公开(公告)号：US20080100340A1
公开(公告)日：2008-05-01
申请号：US11588217
申请日：2006-10-27
申请人： Tzung-Shen Chen , Ti-Wen Chen , Chun-Yu Liao
发明人： Tzung-Shen Chen , Ti-Wen Chen , Chun-Yu Liao
IPC分类号： H03K19/00
CPC分类号： H03K19/09429
摘要： A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.
摘要翻译：低电压互补金属氧化物半导体（CMOS）工艺三态缓冲器包括逻辑器件，偏置器件和开关器件。逻辑器件接收输入信号和使能信号，并产生第一控制信号和第二控制信号。偏置装置接收第一控制信号，从而控制第三控制信号的电压电平。当第二和第三控制信号被使能时，开关装置接收第二和第三控制信号，并分别将输出端耦合到第一外部电压源和第二外部电压源。当使能信号被禁止时，第二和第三控制信号同时被禁止，使得输出端相对于第一和第二外部电压源浮置，并且输出端保持在高阻抗状态。

2. 发明授权

US07432739B2 Low voltage complementary metal oxide semiconductor process tri-state buffer 有权
公开(公告)号：US07432739B2
公开(公告)日：2008-10-07
申请号：US11588217
申请日：2006-10-27
申请人： Tzung-Shen Chen , Ti-Wen Chen , Chun-Yu Liao
发明人： Tzung-Shen Chen , Ti-Wen Chen , Chun-Yu Liao
IPC分类号： H03K19/00 , H03K19/02
CPC分类号： H03K19/09429
摘要： A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.

3. 发明授权

US06529431B1 Rapid equalizing ground line and sense circuit 有权
标题翻译：快速均衡接地线和感测电路
公开(公告)号：US06529431B1
公开(公告)日：2003-03-04
申请号：US09997354
申请日：2001-11-27
申请人： Sheng-Chang Kuo , Ti-Wen Chen , Hsiang-Pang Li
发明人： Sheng-Chang Kuo , Ti-Wen Chen , Hsiang-Pang Li
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/12 , G11C17/126
摘要： A rapid equalizing ground line and sense circuit. The ground line Circuit includes a reference transistor and a plurality of switching circuits. When the ground line signal is disabled, corresponding ground line of the switching circuit couples with the pre-charging bus to initiate a pre-charging operation. If the selected ground line signal is enabled, the selected switching circuit initiates a data sensing operation. If the selected ground line signal is disabled, the corresponding ground line of non-selected switching circuits continues to pre-charge. When the selected ground line signal changes from an enable state to a disable state, the corresponding ground line of the selected switching circuit and corresponding ground line of the non-selected switching circuit are coupled to a voltage source.
摘要翻译：快速均衡接地线和感测电路。接地线电路包括参考晶体管和多个开关电路。当接地线信号被禁止时，开关电路的相应接地线与预充电总线耦合以启动预充电操作。如果选择的接地线信号被使能，则所选择的开关电路启动数据感测操作。如果选择的接地线信号被禁止，则未选择的开关电路的相应接地线继续预充电。当所选择的接地线信号从使能状态变为禁止状态时，所选择的开关电路的对应地线和未选择的开关电路的对应接地线耦合到电压源。

4. 发明申请

US20080043543A1 Method for manufacturing, writing method and reading non-volatile memory 审中-公开
标题翻译：制造方法，写入方法和读取非易失性存储器
公开(公告)号：US20080043543A1
公开(公告)日：2008-02-21
申请号：US11889804
申请日：2007-08-16
申请人： Wei-Chung Chen , Ta-Neng Ho , Ti-Wen Chen , Wei-Ming Chen
发明人： Wei-Chung Chen , Ta-Neng Ho , Ti-Wen Chen , Wei-Ming Chen
IPC分类号： G11C7/00 , H01L21/266
CPC分类号： G11C7/02 , G11C7/1012 , G11C7/1051 , G11C7/1078 , G11C7/1087
摘要： A method of manufacturing, programming and reading a non-volatile memory is provided. First, a to-be-coded memory having a plurality of to-be-coded cells arranged in a array is provided. Next, an implanting resist layer is formed on the to-be-coded memory. Then, a mask is disposed on the to-be-coded memory, wherein the number of the partial to-be-coded cells under the openings of the mask is less than the number of remaining to-be-coded cells. Afterwards, a patterned implanting resist layer is formed according to the mask. Next, the exposed to-be-coded cells are ion-implanted to define a plurality of first cells and second cells, wherein each first cell and each second cell record a second bit state and a first bit state respectively. Then, the to-be-coded memory is inversely defined, such that the first cells and the second cells record the first bit state and the second bit state respectively.
摘要翻译：提供了制造，编程和读取非易失性存储器的方法。首先，提供具有排列成阵列的多个被编码单元的被编码存储器。接下来，在被编码存储器上形成植入抗蚀剂层。然后，将掩模设置在待编码存储器上，其中掩模开口下部分待编码单元的数量小于剩余待编码单元的数量。然后，根据掩模形成图案化的植入抗蚀剂层。接下来，暴露的待编码单元被离子注入以限定多个第一单元和第二单元，其中每个第一单元和每个第二单元分别记录第二位状态和第一位状态。然后，被编码的存储器被反向定义，使得第一单元和第二单元分别记录第一位状态和第二位状态。

5. 发明授权

US06483352B1 Current mirror sense amplifier 有权
标题翻译：电流镜像放大器
公开(公告)号：US06483352B1
公开(公告)日：2002-11-19
申请号：US10047612
申请日：2002-01-14
申请人： Sheng-Chang Kuo , Ti-Wen Chen
发明人： Sheng-Chang Kuo , Ti-Wen Chen
IPC分类号： G11C706
CPC分类号： G11C7/062 , G11C7/067 , G11C2207/063
摘要： A current mirror sense amplifier, with a two-stage current mirror, a first transistor, and a second transistor. The first transistor and the second transistor each have first and second connection terminals. The current mirror has a current input terminal and a current output terminal. The first transistor has a gate electrically connected to a pre-charge voltage. The first connection terminal of the first transistor is electrically connected to a reference voltage. The second transistor has a gate electrically connected to a reference signal. The first connection terminal of the second transistor is electrically connected to the reference voltage. The second connection terminals are connected to the current output terminal in parallel.
摘要翻译：具有两级电流镜的电流镜像读出放大器，第一晶体管和第二晶体管。第一晶体管和第二晶体管都具有第一和第二连接端子。电流镜具有电流输入端和电流输出端。第一晶体管具有电连接到预充电电压的栅极。第一晶体管的第一连接端子电连接到参考电压。第二晶体管具有电连接到参考信号的栅极。第二晶体管的第一连接端子与参考电压电连接。第二连接端子并联连接到电流输出端。

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