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1. 发明申请

US20080100340A1 Low voltage complementary metal oxide semiconductor process tri-state buffer 有权
标题翻译：低电压互补金属氧化物半导体工艺三态缓冲器
公开(公告)号：US20080100340A1
公开(公告)日：2008-05-01
申请号：US11588217
申请日：2006-10-27
申请人： Tzung-Shen Chen , Ti-Wen Chen , Chun-Yu Liao
发明人： Tzung-Shen Chen , Ti-Wen Chen , Chun-Yu Liao
IPC分类号： H03K19/00
CPC分类号： H03K19/09429
摘要： A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.
摘要翻译：低电压互补金属氧化物半导体（CMOS）工艺三态缓冲器包括逻辑器件，偏置器件和开关器件。逻辑器件接收输入信号和使能信号，并产生第一控制信号和第二控制信号。偏置装置接收第一控制信号，从而控制第三控制信号的电压电平。当第二和第三控制信号被使能时，开关装置接收第二和第三控制信号，并分别将输出端耦合到第一外部电压源和第二外部电压源。当使能信号被禁止时，第二和第三控制信号同时被禁止，使得输出端相对于第一和第二外部电压源浮置，并且输出端保持在高阻抗状态。

2. 发明授权

US08902656B2 Plural operation of memory device 有权
标题翻译：存储设备的多种操作
公开(公告)号：US08902656B2
公开(公告)日：2014-12-02
申请号：US13750858
申请日：2013-01-25
申请人： Tzung-Shen Chen , Shuo-Nan Hong , Yi-Ching Liu , Chun-Hsiung Hung
发明人： Tzung-Shen Chen , Shuo-Nan Hong , Yi-Ching Liu , Chun-Hsiung Hung
IPC分类号： G11C11/34 , G11C16/26 , G11C16/34 , G11C16/12 , G11C16/04
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3422 , G11C16/3427 , G11C16/3431
摘要： An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.
摘要翻译：集成电路器件包括半导体衬底，衬底上的第一存储器块，包括NAND存储器单元，在衬底上的第二存储器块，包括NAND存储器单元，以及控制器电路。第一和第二存储器块可配置为响应于第一操作算法存储用于第一数据使用模式的数据，以读取，编程和擦除数据，以及响应于第二操作算法读取数据使用的第二模式，分别编程和擦除数据。控制器电路耦合到第一和第二存储器块，并且被配置为执行第一和第二操作算法，其中在第一操作算法中应用的读操作的字线通过电压处于比第二字的较低电压电平用于在第二操作算法中应用的读操作的线通电压。

3. 发明申请

US20080282120A1 Memory structure, repair system and method for testing the same 审中-公开
标题翻译：内存结构，维修系统和测试方法相同
公开(公告)号：US20080282120A1
公开(公告)日：2008-11-13
申请号：US11798292
申请日：2007-05-11
申请人： Chun-Yu Liao , Tzung-Shen Chen
发明人： Chun-Yu Liao , Tzung-Shen Chen
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： G11C29/42 , G06F11/1008 , G11C29/44 , G11C2029/0411 , G11C2029/1208
摘要： A memory structure is provided. The memory structure includes a memory array, an error correct code (ECC) unit, and a comparator. The memory array includes at least one memory cell being written and storing at least one original data. The ECC unit is for reading at least one tested data from the at least one memory cell, correcting the at least one tested data when there is an error occurred in the at least one tested data and outputting at least one ECC data accordingly. The comparator is for determining whether the at least one original data is substantially the same as the at least one ECC data or not and outputting an output signal indicating whether the at least one memory cell passes or fails.
摘要翻译：提供了存储器结构。存储器结构包括存储器阵列，错误校正码（ECC）单元和比较器。存储器阵列包括被写入的至少一个存储器单元并且存储至少一个原始数据。 ECC单元用于从至少一个存储器单元读取至少一个测试数据，当在至少一个测试数据中发生错误并相应地输出至少一个ECC数据时校正该至少一个测试数据。所述比较器用于确定所述至少一个原始数据是否与所述至少一个ECC数据基本相同，并且输出指示所述至少一个存储器单元是否通过的输出信号。

4. 发明申请

US20130294155A1 PLURAL OPERATION OF MEMORY DEVICE 有权
公开(公告)号：US20130294155A1
公开(公告)日：2013-11-07
申请号：US13750858
申请日：2013-01-25
申请人： Tzung-Shen Chen , Shuo-Nan Hong , Yi-Ching Liu , Chun-Hsiung Hung
发明人： Tzung-Shen Chen , Shuo-Nan Hong , Yi-Ching Liu , Chun-Hsiung Hung
IPC分类号： G11C16/12 , G11C16/26
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3422 , G11C16/3427 , G11C16/3431
摘要： An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.

5. 发明授权

US07432739B2 Low voltage complementary metal oxide semiconductor process tri-state buffer 有权
公开(公告)号：US07432739B2
公开(公告)日：2008-10-07
申请号：US11588217
申请日：2006-10-27
申请人： Tzung-Shen Chen , Ti-Wen Chen , Chun-Yu Liao
发明人： Tzung-Shen Chen , Ti-Wen Chen , Chun-Yu Liao
IPC分类号： H03K19/00 , H03K19/02
CPC分类号： H03K19/09429
摘要： A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.

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