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1. 发明申请

US20190066736A1 NAND CELL ENCODING TO IMPROVE DATA INTEGRITY 审中-公开
公开(公告)号：US20190066736A1
公开(公告)日：2019-02-28
申请号：US15692508
申请日：2017-08-31
申请人： Tyson M. Stichka , Preston Thomson , Scott Anthony Stoller , Christopher Bueb , Jianmin Huang , Kulachet Tanpairoj , Harish Singidi
发明人： Tyson M. Stichka , Preston Thomson , Scott Anthony Stoller , Christopher Bueb , Jianmin Huang , Kulachet Tanpairoj , Harish Singidi
IPC分类号： G11C5/00 , G11C7/04 , G11C16/04 , G11C16/26
CPC分类号： G11C5/005 , G11C7/04 , G11C7/1006 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3459 , G11C2211/5641
摘要： Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.

2. 发明申请

US20190066799A1 SECURE ERASE FOR DATA CORRUPTION 审中-公开
公开(公告)号：US20190066799A1
公开(公告)日：2019-02-28
申请号：US15691584
申请日：2017-08-30
申请人： Ting Luo , Kulachet Tanpairoj , Harish Singidi , Jianmin Huang , Preston Thomson , Sebastien Andre Jean
发明人： Ting Luo , Kulachet Tanpairoj , Harish Singidi , Jianmin Huang , Preston Thomson , Sebastien Andre Jean
IPC分类号： G11C16/16 , G11C16/04 , G11C16/08
CPC分类号： G11C16/16 , G11C11/5635 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/3409 , G11C16/3445 , H01L27/11556 , H01L27/11582
摘要： Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

3. 发明申请

US20210200700A1 PERFORMANCE OF STORAGE SYSTEM BACKGROUND OPERATIONS 有权
公开(公告)号：US20210200700A1
公开(公告)日：2021-07-01
申请号：US17138082
申请日：2020-12-30
申请人： Kulachet Tanpairoj , Jianmin Huang
发明人： Kulachet Tanpairoj , Jianmin Huang
IPC分类号： G06F13/16 , G06F11/30 , G06F12/02 , G06F12/0868 , G06F13/24
摘要： Methods for operating a memory device can include monitoring communications from a host device for a notification that a battery of the host device has entered a charging state and performing a background operation of the memory device responsive to receiving this notification. The notification can be an added functionality incorporated into a standardized interface.

4. 发明授权

US08750045B2 Experience count dependent program algorithm for flash memory 有权
标题翻译：体验闪存的计数依赖程序算法
公开(公告)号：US08750045B2
公开(公告)日：2014-06-10
申请号：US13560896
申请日：2012-07-27
申请人： Jianmin Huang , Kulachet Tanpairoj , Chris Nga Yee Avila , Gautam Ashok Dusija
发明人： Jianmin Huang , Kulachet Tanpairoj , Chris Nga Yee Avila , Gautam Ashok Dusija
IPC分类号： G11C16/06 , G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3481 , G11C16/3495
摘要： In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages.
摘要翻译：在非易失性存储器件中，用于写入和擦除操作的参数根据器件寿命而变化。例如，在使用阶梯波形的编程操作中，可以根据包含所选择的用于写入的物理页的块的擦除程序周期（热计数）的次数来调整初始脉冲的幅度。这种布置可以保持相对新鲜的设备的性能，同时通过在设备老化时通过使用温和波形来延长设备的使用寿命。

5. 发明申请

US20190065080A1 SLC CACHE MANAGEMENT 审中-公开
公开(公告)号：US20190065080A1
公开(公告)日：2019-02-28
申请号：US15690869
申请日：2017-08-30
申请人： Kulachet Tanpairoj , Sebastien Andre Jean , Kishore Kumar Muchherla , Ashutosh Malshe , Jianmin Huang
发明人： Kulachet Tanpairoj , Sebastien Andre Jean , Kishore Kumar Muchherla , Ashutosh Malshe , Jianmin Huang
IPC分类号： G06F3/06 , G06F12/0811
摘要： Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

6. 发明申请

US20140029342A1 EXPERIENCE COUNT DEPENDENT PROGRAM ALGORITHM FOR FLASH MEMORY 有权
标题翻译：闪存存储器的经验计数依赖程序算法
公开(公告)号：US20140029342A1
公开(公告)日：2014-01-30
申请号：US13560896
申请日：2012-07-27
申请人： Jianmin Huang , Kulachet Tanpairoj , Chris Nga Yee Avila , Gautam Ahok Dusija
发明人： Jianmin Huang , Kulachet Tanpairoj , Chris Nga Yee Avila , Gautam Ahok Dusija
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3481 , G11C16/3495
摘要： In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages.
摘要翻译：在非易失性存储器件中，用于写入和擦除操作的参数根据器件寿命而变化。例如，在使用阶梯波形的编程操作中，可以根据包含所选择的用于写入的物理页的块的擦除程序周期（热计数）的次数来调整初始脉冲的幅度。这种布置可以保持相对新鲜的设备的性能，同时通过在设备老化时通过使用温和波形来延长设备的使用寿命。

7. 发明授权

US09053808B2 Flash memory with targeted read scrub algorithm 有权
标题翻译：具有目标读取擦除算法的闪存
公开(公告)号：US09053808B2
公开(公告)日：2015-06-09
申请号：US13529522
申请日：2012-06-21
申请人： Steven T. Sprouse , Alexandra Bauche , Yichao Huang , Jian Chen , Jianmin Huang , Dana Lee
发明人： Steven T. Sprouse , Alexandra Bauche , Yichao Huang , Jian Chen , Jianmin Huang , Dana Lee
IPC分类号： G06F11/00 , G11C16/34 , G11B20/18
CPC分类号： G11C16/3418 , G11B20/18 , G11B20/1883 , G11C16/3427 , G11C16/3431
摘要： A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.
摘要翻译：已经描述了用于抵消和校正闪速存储器块中的读取干扰效应的方法和系统。该方法可以包括存储器系统的控制器的步骤，其以期望的间隔仅在块中的一个目标字线的一部分上执行读取擦除扫描。控制器可以基于响应于每个接收的主机读取命令而计算的概率确定来计算是否需要读取擦除扫描。然后，如果在满足或超过预定阈值的目标字线中检测到多个错误，则控制器然后可以将与目标字线相关联的块放置到刷新队列中。块刷新过程可以包括在后台操作期间将数据从块复制到新块中。

8. 发明授权

US08468294B2 Non-volatile memory with multi-gear control using on-chip folding of data 有权
标题翻译：具有多档位控制的非易失性存储使用片上数据折叠
公开(公告)号：US08468294B2
公开(公告)日：2013-06-18
申请号：US12642611
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
IPC分类号： G06F3/06 , G11C11/56
CPC分类号： G06F3/0608 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C7/1042 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分，其中数据以多状态格式存储。存储器系统从主机接收数据，并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括从第一部分读取数据的部分，将数据重写成第二部分使用多状态编程操作的非易失性存储器的一部分。控制器根据多种模式之一确定操作存储器系统。这些模式包括第一模式，其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式，其中相对于二进制写入操作的数量的折叠操作的数量存储器的第一部分在高于第一模式下执行。然后，存储器系统根据确定的模式进行操作。存储器系统还可以包括第三模式，其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。

9. 发明申请

US20120311244A1 Balanced Performance for On-Chip Folding of Non-Volatile Memories 有权
标题翻译：非易失性存储器片上折叠的平衡性能
公开(公告)号：US20120311244A1
公开(公告)日：2012-12-06
申请号：US13491879
申请日：2012-06-08
申请人： Yichao Huang , Jianmin Huang , Gautam Ashok Dusija , Oleg Kragel
发明人： Yichao Huang , Jianmin Huang , Gautam Ashok Dusija , Oleg Kragel
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C7/1042 , G11C11/5628 , G11C16/0483 , G11C2211/5641
摘要： A non-volatile memory system receives and stores host data. As the memory system receives host data, it initially writes the data in a binary format and then subsequently performs an on-chip folding operation on the data, storing the data in a multi-state format. The memory system interleaves the phases of the folding operations so that performance is made more uniform across allocation units, where the host stores data according to allocation units. The memory system also can perform the binary and subsequent on-chip folding operations on multiple memory planes in parallel, where the controller also balances the operations so that performance is made more uniform between planes with respect to allocation units as the data is received from the host. To further maintain performance, the memory system uses a free block list having a reserve portion that is only accessible for a specified set of commands.
摘要翻译：非易失性存储器系统接收并存储主机数据。当存储器系统接收主机数据时，它首先以二进制格式写入数据，然后对数据执行片上折叠操作，以多状态格式存储数据。存储器系统对折叠操作的相位进行交织，使得在分配单元之间使得性能更均匀，其中主机根据分配单元存储数据。存储器系统还可以并行地在多个存储器平面上执行二进制和随后的片上折叠操作，其中控制器还平衡操作，使得在相对于分配单元的平面之间的性能更均匀，因为从主办。为了进一步维持性能，内存系统使用一个空闲块列表，该列表具有一个只能用于一组指定命令的预留部分。

10. 发明申请

US20110153911A1 METHOD AND SYSTEM FOR ACHIEVING DIE PARALLELISM THROUGH BLOCK INTERLEAVING 有权
标题翻译：通过块交互实现平行排列的方法和系统
公开(公告)号：US20110153911A1
公开(公告)日：2011-06-23
申请号：US12642181
申请日：2009-12-18
申请人： Steven Sprouse , Chris Avila , Jianmin Huang
发明人： Steven Sprouse , Chris Avila , Jianmin Huang
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G11C11/5628 , G06F12/0246 , G06F12/0851 , G06F12/0871 , G06F2212/2022 , G06F2212/214 , G06F2212/222 , G06F2212/284 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G11C7/1042 , G11C16/0483 , G11C2207/2245 , G11C2211/5641 , G11C2211/5643
摘要： A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write sequentially addressed data to the cache storage area of a first die. The controller, after writing sequentially addressed data to the cache storage area of the first die equal to a block of the main storage area of the first die, writes additional data to a cache storage area of a next die until sequentially addressed data is written into the cache area of the next die equal to a block of the main storage area. The cache storage area may be copied to the main storage area on the first die while the cache storage area is written to on the next die.
摘要翻译：通过块交织实现管芯并行的方法和系统包括具有多个非易失性存储器管芯的非易失性存储器，其中每个管芯具有缓存存储区域和主存储区域。控制器被配置为接收数据并将顺序寻址的数据写入到第一管芯的缓存存储区域。控制器在将顺序寻址的数据写入与第一管芯的主存储区域的块相等的第一管芯的高速缓存存储区域之后，将附加数据写入下一个管芯的高速缓存存储区域，直到顺序寻址的数据被写入下一个芯片的高速缓存区域等于主存储区域的块。高速缓存存储区域可以被复制到第一裸片上的主存储区域，而缓存存储区域被写入到下一个芯片上。

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