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1. 发明授权

US08468294B2 Non-volatile memory with multi-gear control using on-chip folding of data 有权
标题翻译：具有多档位控制的非易失性存储使用片上数据折叠
公开(公告)号：US08468294B2
公开(公告)日：2013-06-18
申请号：US12642611
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
IPC分类号： G06F3/06 , G11C11/56
CPC分类号： G06F3/0608 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C7/1042 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分，其中数据以多状态格式存储。存储器系统从主机接收数据，并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括从第一部分读取数据的部分，将数据重写成第二部分使用多状态编程操作的非易失性存储器的一部分。控制器根据多种模式之一确定操作存储器系统。这些模式包括第一模式，其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式，其中相对于二进制写入操作的数量的折叠操作的数量存储器的第一部分在高于第一模式下执行。然后，存储器系统根据确定的模式进行操作。存储器系统还可以包括第三模式，其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。

2. 发明申请

US20110153913A1 Non-Volatile Memory with Multi-Gear Control Using On-Chip Folding of Data 有权
标题翻译：使用片上数据折叠的多档位控制的非易失性存储器
公开(公告)号：US20110153913A1
公开(公告)日：2011-06-23
申请号：US12642611
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F3/0608 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C7/1042 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分，其中数据以多状态格式存储。存储器系统从主机接收数据，并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括从第一部分读取数据的部分，将数据重写成第二部分使用多状态编程操作的非易失性存储器的一部分。控制器根据多种模式之一确定操作存储器系统。这些模式包括第一模式，其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式，其中相对于二进制写入操作的数量的折叠操作的数量存储器的第一部分在高于第一模式下执行。然后，存储器系统根据确定的模式进行操作。存储器系统还可以包括第三模式，其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。

3. 发明授权

US08144512B2 Data transfer flows for on-chip folding 有权
标题翻译：数据传输流程用于片上折叠
公开(公告)号：US08144512B2
公开(公告)日：2012-03-27
申请号：US12642649
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Neil David Hutchinson , Sergey Anatolievich Gorobets
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Neil David Hutchinson , Sergey Anatolievich Gorobets
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G06F12/0246 , G06F2212/7203 , G11C7/1042 , G11C16/10 , G11C2211/5641 , G11C2211/5643
摘要： A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the portions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括易失性缓冲存储器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分，以及第二部分，状态格式。当将数据写入非易失性存储器时，将数据从存储在缓冲存储器中的主机接收，从缓冲存储器传送到非易失性存储器电路的读/写寄存器，然后从读/ 使用二进制写操作将寄存器写入非易失性存储器电路的第一部分。然后将数据的部分随后从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括将第一部分中的多个位置的数据的部分读入读取 /写寄存器，并且将数据的部分的数据从读/写寄存器执行到非易失性存储器的第二部分的位置的多状态编程操作。多状态编程操作包括第一阶段和第二阶段，并且在多状态编程操作的阶段之间执行二进制写入操作中的一个或多个。

4. 发明申请

US20110149650A1 Data Transfer Flows for On-Chip Folding 有权
标题翻译：片上折叠数据传输流程
公开(公告)号：US20110149650A1
公开(公告)日：2011-06-23
申请号：US12642649
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Neil David Hutchison , Sergey Anatolievich Gorobets
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Neil David Hutchison , Sergey Anatolievich Gorobets
IPC分类号： G11C16/04 , G11C14/00
CPC分类号： G11C11/5628 , G06F12/0246 , G06F2212/7203 , G11C7/1042 , G11C16/10 , G11C2211/5641 , G11C2211/5643
摘要： A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括易失性缓冲存储器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分，以及第二部分，状态格式。当将数据写入非易失性存储器时，将数据从存储在缓冲存储器中的主机接收，从缓冲存储器传送到非易失性存储器电路的读/写寄存器，然后从读/ 使用二进制写操作将寄存器写入非易失性存储器电路的第一部分。然后将数据的部分随后从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括将第一部分中的多个位置的数据的部分读入读取 /写入寄存器，并且将数据从读/写寄存器执行到多状态编程操作到非易失性存储器的第二部分的位置。多状态编程操作包括第一阶段和第二阶段，并且在多状态编程操作的阶段之间执行二进制写入操作中的一个或多个。

5. 发明授权

US08634239B2 Hybrid multi-level cell programming sequences 有权
标题翻译：混合多级单元编程序列
公开(公告)号：US08634239B2
公开(公告)日：2014-01-21
申请号：US13339017
申请日：2011-12-28
申请人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
发明人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10
摘要： A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC.
摘要翻译：存储器件实现用于将数据写入多级单元（MLC）的混合编程序列。存储器件获得指定的数据以写入MLC，并在多种不同的编程技术之间进行选择来写入指定的数据。每个编程技术在MLC中建立代表多个数据位的电荷配置。存储器件使用所选的编程技术将指定的数据写入MLC。在一个实现中，编程技术包括鲁棒编程技术，其在写入中止指定数据的情况下保留MLC中的先前写入的数据，以及具有比鲁棒编程技术更高的平均性能的附加编程技术。可以基于各种各样的标准来进行选择，包括数据是否已经被预先写入包括MLC的块。

6. 发明申请

US20130170293A1 HYBRID MULTI-LEVEL CELL PROGRAMMING SEQUENCES 有权
标题翻译：混合多级细胞编程序列
公开(公告)号：US20130170293A1
公开(公告)日：2013-07-04
申请号：US13339017
申请日：2011-12-28
申请人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
发明人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/10
摘要： A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC.
摘要翻译：存储器件实现用于将数据写入多级单元（MLC）的混合编程序列。存储器件获得指定的数据以写入MLC，并在多种不同的编程技术之间进行选择来写入指定的数据。每个编程技术在MLC中建立代表多个数据位的电荷配置。存储器件使用所选的编程技术将指定的数据写入MLC。在一个实现中，编程技术包括鲁棒编程技术，其在写入中止指定数据的情况下保留MLC中的先前写入的数据，以及具有比鲁棒编程技术更高的平均性能的附加编程技术。可以基于各种各样的标准来进行选择，包括数据是否已经被预先写入包括MLC的块。

7. 发明申请

US20110099460A1 Non-Volatile Memory And Method With Post-Write Read And Adaptive Re-Write To Manage Errors 有权
标题翻译：非易失性存储器和具有后写入读取和自适应重写的方法来管理错误
公开(公告)号：US20110099460A1
公开(公告)日：2011-04-28
申请号：US12642728
申请日：2009-12-18
申请人： Gautam Ashok Dusija , Jian Chen , Chris Avila , Jianmin Huang , Lee M. Gavens
发明人： Gautam Ashok Dusija , Jian Chen , Chris Avila , Jianmin Huang , Lee M. Gavens
IPC分类号： G11C29/52 , G06F11/10 , G06F12/16 , G06F12/00
CPC分类号： G11C11/5621 , G11C16/10 , G11C16/349 , G11C16/3495 , G11C29/00 , G11C2211/5641
摘要： Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.
摘要翻译：非易失性存储器中的数据错误不可避免地随着使用而增加，并且每个单元存储更高密度的位。存储器被配置为具有以较小误差但是较低密度存储器操作的第一部分，以及以较高密度但较不牢固的存储器操作的第二部分。在将第一部分复制到第二部分之前，输入数据被写入并分级。错误管理提供检查复制数据的质量是否存在过多的错误位。在第二部分中的不同位置重复复印和检查，直到满足预定质量或者数量或重复超过预定限度。当存储器是新的，几乎没有或没有错误时，错误管理不开始，但是在内存已经老化到由其经历的擦除/程序循环的数量确定的预定量之后开始。

8. 发明授权

US08423866B2 Non-volatile memory and method with post-write read and adaptive re-write to manage errors 有权
标题翻译：非易失性存储器和具有后写入读取和自适应重写的方法来管理错误
公开(公告)号：US08423866B2
公开(公告)日：2013-04-16
申请号：US12642728
申请日：2009-12-18
申请人： Gautam Ashok Dusija , Jian Chen , Chris Avila , Jianmin Huang , Lee M. Gavens
发明人： Gautam Ashok Dusija , Jian Chen , Chris Avila , Jianmin Huang , Lee M. Gavens
IPC分类号： G06F11/00
CPC分类号： G11C11/5621 , G11C16/10 , G11C16/349 , G11C16/3495 , G11C29/00 , G11C2211/5641
摘要： Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.
摘要翻译：非易失性存储器中的数据错误不可避免地随着使用而增加，并且每个单元存储更高密度的位。存储器被配置为具有以较小误差但是较低密度存储器操作的第一部分，以及以较高密度但较不牢固的存储器操作的第二部分。在将第一部分复制到第二部分之前，输入数据被写入并分级。错误管理提供检查复制数据的质量是否存在过多的错误位。在第二部分中的不同位置重复复印和检查，直到满足预定质量或者数量或重复超过预定限度。当存储器是新的，几乎没有或没有错误时，错误管理不开始，但是在内存已经老化到由其经历的擦除/程序循环的数量确定的预定量之后开始。

9. 发明申请

US20110153911A1 METHOD AND SYSTEM FOR ACHIEVING DIE PARALLELISM THROUGH BLOCK INTERLEAVING 有权
标题翻译：通过块交互实现平行排列的方法和系统
公开(公告)号：US20110153911A1
公开(公告)日：2011-06-23
申请号：US12642181
申请日：2009-12-18
申请人： Steven Sprouse , Chris Avila , Jianmin Huang
发明人： Steven Sprouse , Chris Avila , Jianmin Huang
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G11C11/5628 , G06F12/0246 , G06F12/0851 , G06F12/0871 , G06F2212/2022 , G06F2212/214 , G06F2212/222 , G06F2212/284 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G11C7/1042 , G11C16/0483 , G11C2207/2245 , G11C2211/5641 , G11C2211/5643
摘要： A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write sequentially addressed data to the cache storage area of a first die. The controller, after writing sequentially addressed data to the cache storage area of the first die equal to a block of the main storage area of the first die, writes additional data to a cache storage area of a next die until sequentially addressed data is written into the cache area of the next die equal to a block of the main storage area. The cache storage area may be copied to the main storage area on the first die while the cache storage area is written to on the next die.
摘要翻译：通过块交织实现管芯并行的方法和系统包括具有多个非易失性存储器管芯的非易失性存储器，其中每个管芯具有缓存存储区域和主存储区域。控制器被配置为接收数据并将顺序寻址的数据写入到第一管芯的缓存存储区域。控制器在将顺序寻址的数据写入与第一管芯的主存储区域的块相等的第一管芯的高速缓存存储区域之后，将附加数据写入下一个管芯的高速缓存存储区域，直到顺序寻址的数据被写入下一个芯片的高速缓存区域等于主存储区域的块。高速缓存存储区域可以被复制到第一裸片上的主存储区域，而缓存存储区域被写入到下一个芯片上。

10. 发明申请

US20110010484A1 OPTIMIZED PAGE PROGRAMMING ORDER FOR NON-VOLATILE MEMORY 有权
标题翻译：优化的非易失性存储器页面编程订单
公开(公告)号：US20110010484A1
公开(公告)日：2011-01-13
申请号：US12499219
申请日：2009-07-08
申请人： Steven Sprouse , Jianmin Huang , Chris Avila , Yichao Huang , Emilio Yero
发明人： Steven Sprouse , Jianmin Huang , Chris Avila , Yichao Huang , Emilio Yero
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G11C11/5628 , G11C2211/5648
摘要： During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.
摘要翻译：在非易失性存储系统中的编程数据传输过程中，数据的记录单元从主机传送到诸如存储卡的存储设备。对于每个记录单元，数据页按照这样的顺序排列，使得在写入时间较少的页面之前提供需要更长时间写入存储器件的存储器阵列的页面。由于发生更大程度的并行处理，记录单元的整体编程时间减少。当将编程所需的时间更长的页面编程到存储器阵列时，将编程所需的较少时间的页面传送到存储器件。编程完成后，存储器信号通知主机传送下一个记录单元。数据页可以包括下页，中页和上页。

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