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1. 发明授权

US08750045B2 Experience count dependent program algorithm for flash memory 有权
标题翻译：体验闪存的计数依赖程序算法
公开(公告)号：US08750045B2
公开(公告)日：2014-06-10
申请号：US13560896
申请日：2012-07-27
申请人： Jianmin Huang , Kulachet Tanpairoj , Chris Nga Yee Avila , Gautam Ashok Dusija
发明人： Jianmin Huang , Kulachet Tanpairoj , Chris Nga Yee Avila , Gautam Ashok Dusija
IPC分类号： G11C16/06 , G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3481 , G11C16/3495
摘要： In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages.
摘要翻译：在非易失性存储器件中，用于写入和擦除操作的参数根据器件寿命而变化。例如，在使用阶梯波形的编程操作中，可以根据包含所选择的用于写入的物理页的块的擦除程序周期（热计数）的次数来调整初始脉冲的幅度。这种布置可以保持相对新鲜的设备的性能，同时通过在设备老化时通过使用温和波形来延长设备的使用寿命。

2. 发明申请

US20140029342A1 EXPERIENCE COUNT DEPENDENT PROGRAM ALGORITHM FOR FLASH MEMORY 有权
标题翻译：闪存存储器的经验计数依赖程序算法
公开(公告)号：US20140029342A1
公开(公告)日：2014-01-30
申请号：US13560896
申请日：2012-07-27
申请人： Jianmin Huang , Kulachet Tanpairoj , Chris Nga Yee Avila , Gautam Ahok Dusija
发明人： Jianmin Huang , Kulachet Tanpairoj , Chris Nga Yee Avila , Gautam Ahok Dusija
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3481 , G11C16/3495
摘要： In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages.
摘要翻译：在非易失性存储器件中，用于写入和擦除操作的参数根据器件寿命而变化。例如，在使用阶梯波形的编程操作中，可以根据包含所选择的用于写入的物理页的块的擦除程序周期（热计数）的次数来调整初始脉冲的幅度。这种布置可以保持相对新鲜的设备的性能，同时通过在设备老化时通过使用温和波形来延长设备的使用寿命。

3. 发明申请

US20120284574A1 Non-Volatile Memory and Method Having Efficient On-Chip Block-Copying with Controlled Error Rate 有权
标题翻译：非易失性存储器和具有有效的片上块复制与受控错误率的方法
公开(公告)号：US20120284574A1
公开(公告)日：2012-11-08
申请号：US13457247
申请日：2012-04-26
申请人： Chris Nga Yee Avila , Jianmin Huang , Lee M. Gavens , Idan Alrod
发明人： Chris Nga Yee Avila , Jianmin Huang , Lee M. Gavens , Idan Alrod
IPC分类号： G06F11/00 , H03M13/05
CPC分类号： G11C16/28 , G11C29/50004 , G11C2211/5634 , G11C2211/5641
摘要： A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget.
摘要翻译：具有作为用于高密度存储的MLC块的写高速缓存的SLC块的非易失性存储器芯片需要将SLC块复制或折叠到MLC块中。为了避免在控制器芯片进行ECC检查的整个SLC块的页面中耗费时间的切换，仅检查小样本。通过尝试不同的读取点动态地确定用于读取SLC块样本中的存储单元的最佳读取点，以便在错误预算内读取数据。一旦确定了最佳读取点，它将用于读取整个SLC块而无需进一步的错误检查。然后可以将SLC块复制（盲目折叠）到MLC块，其置信度在错误预算之内。

4. 发明授权

US08713380B2 Non-volatile memory and method having efficient on-chip block-copying with controlled error rate 有权
标题翻译：非易失性存储器和方法具有有效的片内块复制和受控错误率
公开(公告)号：US08713380B2
公开(公告)日：2014-04-29
申请号：US13457247
申请日：2012-04-26
申请人： Chris Nga Yee Avila , Jianmin Huang , Lee M. Gavens , Idan Alrod
发明人： Chris Nga Yee Avila , Jianmin Huang , Lee M. Gavens , Idan Alrod
IPC分类号： G06F11/00
CPC分类号： G11C16/28 , G11C29/50004 , G11C2211/5634 , G11C2211/5641
摘要： A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget.
摘要翻译：具有作为用于高密度存储的MLC块的写高速缓存的SLC块的非易失性存储器芯片需要将SLC块复制或折叠到MLC块中。为了避免在控制器芯片进行ECC检查的整个SLC块的页面中耗费时间的切换，仅检查小样本。通过尝试不同的读取点动态地确定用于读取SLC块样本中的存储单元的最佳读取点，以便在错误预算内读取数据。一旦确定了最佳读取点，它将用于读取整个SLC块而无需进一步的错误检查。然后可以将SLC块复制（盲目折叠）到MLC块，其置信度在错误预算之内。

5. 发明申请

US20110099460A1 Non-Volatile Memory And Method With Post-Write Read And Adaptive Re-Write To Manage Errors 有权
标题翻译：非易失性存储器和具有后写入读取和自适应重写的方法来管理错误
公开(公告)号：US20110099460A1
公开(公告)日：2011-04-28
申请号：US12642728
申请日：2009-12-18
申请人： Gautam Ashok Dusija , Jian Chen , Chris Avila , Jianmin Huang , Lee M. Gavens
发明人： Gautam Ashok Dusija , Jian Chen , Chris Avila , Jianmin Huang , Lee M. Gavens
IPC分类号： G11C29/52 , G06F11/10 , G06F12/16 , G06F12/00
CPC分类号： G11C11/5621 , G11C16/10 , G11C16/349 , G11C16/3495 , G11C29/00 , G11C2211/5641
摘要： Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.
摘要翻译：非易失性存储器中的数据错误不可避免地随着使用而增加，并且每个单元存储更高密度的位。存储器被配置为具有以较小误差但是较低密度存储器操作的第一部分，以及以较高密度但较不牢固的存储器操作的第二部分。在将第一部分复制到第二部分之前，输入数据被写入并分级。错误管理提供检查复制数据的质量是否存在过多的错误位。在第二部分中的不同位置重复复印和检查，直到满足预定质量或者数量或重复超过预定限度。当存储器是新的，几乎没有或没有错误时，错误管理不开始，但是在内存已经老化到由其经历的擦除/程序循环的数量确定的预定量之后开始。

6. 发明申请

US20120311244A1 Balanced Performance for On-Chip Folding of Non-Volatile Memories 有权
标题翻译：非易失性存储器片上折叠的平衡性能
公开(公告)号：US20120311244A1
公开(公告)日：2012-12-06
申请号：US13491879
申请日：2012-06-08
申请人： Yichao Huang , Jianmin Huang , Gautam Ashok Dusija , Oleg Kragel
发明人： Yichao Huang , Jianmin Huang , Gautam Ashok Dusija , Oleg Kragel
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C7/1042 , G11C11/5628 , G11C16/0483 , G11C2211/5641
摘要： A non-volatile memory system receives and stores host data. As the memory system receives host data, it initially writes the data in a binary format and then subsequently performs an on-chip folding operation on the data, storing the data in a multi-state format. The memory system interleaves the phases of the folding operations so that performance is made more uniform across allocation units, where the host stores data according to allocation units. The memory system also can perform the binary and subsequent on-chip folding operations on multiple memory planes in parallel, where the controller also balances the operations so that performance is made more uniform between planes with respect to allocation units as the data is received from the host. To further maintain performance, the memory system uses a free block list having a reserve portion that is only accessible for a specified set of commands.
摘要翻译：非易失性存储器系统接收并存储主机数据。当存储器系统接收主机数据时，它首先以二进制格式写入数据，然后对数据执行片上折叠操作，以多状态格式存储数据。存储器系统对折叠操作的相位进行交织，使得在分配单元之间使得性能更均匀，其中主机根据分配单元存储数据。存储器系统还可以并行地在多个存储器平面上执行二进制和随后的片上折叠操作，其中控制器还平衡操作，使得在相对于分配单元的平面之间的性能更均匀，因为从主办。为了进一步维持性能，内存系统使用一个空闲块列表，该列表具有一个只能用于一组指定命令的预留部分。

7. 发明授权

US08725935B2 Balanced performance for on-chip folding of non-volatile memories 有权
标题翻译：平衡性能，用于非易失性存储器的片上折叠
公开(公告)号：US08725935B2
公开(公告)日：2014-05-13
申请号：US13491879
申请日：2012-06-08
申请人： Yichao Huang , Jianmin Huang , Gautam Ashok Dusija , Oleg Kragel
发明人： Yichao Huang , Jianmin Huang , Gautam Ashok Dusija , Oleg Kragel
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C7/1042 , G11C11/5628 , G11C16/0483 , G11C2211/5641
摘要： A non-volatile memory system receives and stores host data. As the memory system receives host data, it initially writes the data in a binary format and then subsequently performs an on-chip folding operation on the data, storing the data in a multi-state format. The memory system interleaves the phases of the folding operations, where the host stores data according to allocation units. The memory system also can perform the binary and subsequent on-chip folding operations on multiple memory planes in parallel, where the controller also balances the operations. When the memory system needs a memory block for the writing of data, it selects blocks from a free block list, where the free block list includes a reserve portion that is only accessible for a specified set of commands.
摘要翻译：非易失性存储器系统接收并存储主机数据。当存储器系统接收主机数据时，它首先以二进制格式写入数据，然后对数据执行片上折叠操作，以多状态格式存储数据。存储器系统交织折叠操作的阶段，其中主机根据分配单元存储数据。存储器系统还可以并行地在多个存储器平面上执行二进制和随后的片上折叠操作，其中控制器还平衡操作。当存储器系统需要用于写入数据的存储器块时，它从空闲块列表中选择块，其中空闲块列表包括仅可用于指定的一组命令的预留部分。

8. 发明授权

US08423866B2 Non-volatile memory and method with post-write read and adaptive re-write to manage errors 有权
标题翻译：非易失性存储器和具有后写入读取和自适应重写的方法来管理错误
公开(公告)号：US08423866B2
公开(公告)日：2013-04-16
申请号：US12642728
申请日：2009-12-18
申请人： Gautam Ashok Dusija , Jian Chen , Chris Avila , Jianmin Huang , Lee M. Gavens
发明人： Gautam Ashok Dusija , Jian Chen , Chris Avila , Jianmin Huang , Lee M. Gavens
IPC分类号： G06F11/00
CPC分类号： G11C11/5621 , G11C16/10 , G11C16/349 , G11C16/3495 , G11C29/00 , G11C2211/5641
摘要： Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.
摘要翻译：非易失性存储器中的数据错误不可避免地随着使用而增加，并且每个单元存储更高密度的位。存储器被配置为具有以较小误差但是较低密度存储器操作的第一部分，以及以较高密度但较不牢固的存储器操作的第二部分。在将第一部分复制到第二部分之前，输入数据被写入并分级。错误管理提供检查复制数据的质量是否存在过多的错误位。在第二部分中的不同位置重复复印和检查，直到满足预定质量或者数量或重复超过预定限度。当存储器是新的，几乎没有或没有错误时，错误管理不开始，但是在内存已经老化到由其经历的擦除/程序循环的数量确定的预定量之后开始。

9. 发明申请

US20210200700A1 PERFORMANCE OF STORAGE SYSTEM BACKGROUND OPERATIONS 有权
公开(公告)号：US20210200700A1
公开(公告)日：2021-07-01
申请号：US17138082
申请日：2020-12-30
申请人： Kulachet Tanpairoj , Jianmin Huang
发明人： Kulachet Tanpairoj , Jianmin Huang
IPC分类号： G06F13/16 , G06F11/30 , G06F12/02 , G06F12/0868 , G06F13/24
摘要： Methods for operating a memory device can include monitoring communications from a host device for a notification that a battery of the host device has entered a charging state and performing a background operation of the memory device responsive to receiving this notification. The notification can be an added functionality incorporated into a standardized interface.

10. 发明申请

US20190066736A1 NAND CELL ENCODING TO IMPROVE DATA INTEGRITY 审中-公开
公开(公告)号：US20190066736A1
公开(公告)日：2019-02-28
申请号：US15692508
申请日：2017-08-31
申请人： Tyson M. Stichka , Preston Thomson , Scott Anthony Stoller , Christopher Bueb , Jianmin Huang , Kulachet Tanpairoj , Harish Singidi
发明人： Tyson M. Stichka , Preston Thomson , Scott Anthony Stoller , Christopher Bueb , Jianmin Huang , Kulachet Tanpairoj , Harish Singidi
IPC分类号： G11C5/00 , G11C7/04 , G11C16/04 , G11C16/26
CPC分类号： G11C5/005 , G11C7/04 , G11C7/1006 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3459 , G11C2211/5641
摘要： Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.

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