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1. 发明授权

US08546269B2 Top-down nanowire thinning processes 失效
标题翻译：自上而下的纳米线稀疏过程
公开(公告)号：US08546269B2
公开(公告)日：2013-10-01
申请号：US12417936
申请日：2009-04-03
申请人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
发明人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
IPC分类号： H01L21/302 , H01L21/461 , H01L29/06
CPC分类号： H01L21/02238 , B82Y10/00 , B82Y30/00 , H01L21/02255 , H01L21/30604 , H01L29/0665 , H01L29/0676 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.
摘要翻译：提供了制造基于纳米线的器件的技术。一方面，提供一种制造半导体器件的方法，包括以下步骤。提供了在掩埋氧化物（BOX）层上方具有绝缘体上硅（SOI）层的晶片。将纳米线和焊盘蚀刻到SOI层中以形成阶梯状结构，其中焊盘附着在纳米线的相对端。 BOX层在纳米线下面被切下。纳米线和焊盘与氧化气体接触，以在通过氧化在纳米线上产生硅消耗速率与硅消耗速率之比的条件下，在纳米线和焊盘中氧化硅，焊盘上的氧化从约0.75降至约1.25。在使纳米线和焊盘与氧化气体接触之前，可以统一所有纳米线中的宽度与厚度的纵横比。

2. 发明申请

US20100255680A1 Top-Down Nanowire Thinning Processes 失效
标题翻译：自上而下的纳米线变薄过程
公开(公告)号：US20100255680A1
公开(公告)日：2010-10-07
申请号：US12417936
申请日：2009-04-03
申请人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
发明人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
IPC分类号： H01L21/306
CPC分类号： H01L21/02238 , B82Y10/00 , B82Y30/00 , H01L21/02255 , H01L21/30604 , H01L29/0665 , H01L29/0676 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.
摘要翻译：提供了制造基于纳米线的器件的技术。一方面，提供一种制造半导体器件的方法，包括以下步骤。提供了在掩埋氧化物（BOX）层上方具有绝缘体上硅（SOI）层的晶片。将纳米线和焊盘蚀刻到SOI层中以形成阶梯状结构，其中焊盘附着在纳米线的相对端。 BOX层在纳米线下面被切下。纳米线和焊盘与氧化气体接触，以在通过氧化在纳米线上产生硅消耗速率与硅消耗速率之比的条件下，在纳米线和焊盘中氧化硅，焊盘上的氧化从约0.75降至约1.25。在使纳米线和焊盘与氧化气体接触之前，可以统一所有纳米线中的宽度与厚度的纵横比。

3. 发明申请

US20100295020A1 Method For Forming A Robust Top-Down Silicon Nanowire Structure Using A Conformal Nitride And Such Structure 有权
标题翻译：使用保形氮化物和这种结构形成坚固的自上而下的硅纳米线结构的方法
公开(公告)号：US20100295020A1
公开(公告)日：2010-11-25
申请号：US12469304
申请日：2009-05-20
申请人： Tymon Barwicz , Lidija Sekaric , Jeffrey W. Sleight
发明人： Tymon Barwicz , Lidija Sekaric , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L21/18
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： A nanowire product and process for fabricating it has a wafer with a buried oxide (BOX) upper layer in which a well is formed and the ends of a nanowire are on the BOX layer forming a beam that spans the well. A mask coating is formed on the upper surface of the BOX layer leaving an uncoated window over a center part of the beam and also forming a mask coating around the beam intermediate ends between each end of the beam center part and a side wall of the well. Applying oxygen through the window thins the beam center part while leaving the wire intermediate ends over the well thicker and having a generally arched shape. A thermal oxide coating can be placed on the wire and also the mask on the BOX layer before oxidation.
摘要翻译：纳米线产品及其制造方法具有具有掩埋氧化物（BOX）上层的晶片，其中形成阱，并且纳米线的端部在BOX层上形成跨越阱的束。掩模涂层形成在BOX层的上表面上，在光束的中心部分上留下未涂覆的窗口，并且还在光束中心部分的每个端部和阱的侧壁之间的光束中间端部周围形成掩模涂层。通过窗户施加氧气，使梁中心部分离开，同时将钢丝中间端部覆盖在较厚的孔上并具有大致拱形的形状。在氧化之前，可以将热氧化物涂层放置在导线上以及BOX层上的掩模上。

4. 发明申请

US20110175063A1 SEMICONDUCTOR NANOWIRES HAVING MOBILITY-OPTIMIZED ORIENTATIONS 有权
标题翻译：具有移动优化方位的半导体纳米级
公开(公告)号：US20110175063A1
公开(公告)日：2011-07-21
申请号：US13075551
申请日：2011-03-30
申请人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
发明人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
IPC分类号： H01L29/775
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , H01L29/0673 , H01L29/125 , H01L29/42392 , H01L29/78696
摘要： Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.
摘要翻译：通过在电介质材料层上的半导体层进行平版印刷图案，形成各自包括半导体连接部分和两个邻接焊盘部分的原型半导体结构。半导体连接部分的侧壁被定向为使第一类型半导体结构的空穴迁移率最大化，并使第二类型半导体结构的电子迁移率最大化。通过半导体结构的氧化来减薄半导体连接部分的宽度，以不同的速率降低不同的晶体取向。半导体连接部分的宽度是预定的，使得在半导体连接部分的侧壁上的不同量的薄化导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。通过补偿不同晶面的不同稀释速率，可以为不同的晶体取向形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不充分变薄。

5. 发明授权

US07943530B2 Semiconductor nanowires having mobility-optimized orientations 有权
标题翻译：具有移动性优化取向的半导体纳米线
公开(公告)号：US07943530B2
公开(公告)日：2011-05-17
申请号：US12417796
申请日：2009-04-03
申请人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
发明人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , H01L29/0673 , H01L29/125 , H01L29/42392 , H01L29/78696
摘要： Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.
摘要翻译：通过在电介质材料层上的半导体层进行平版印刷图案，形成各自包括半导体连接部分和两个邻接焊盘部分的原型半导体结构。半导体连接部分的侧壁被定向为使第一类型半导体结构的空穴迁移率最大化，并使第二类型半导体结构的电子迁移率最大化。通过半导体结构的氧化来减薄半导体连接部分的宽度，以不同的速率降低不同的晶体取向。半导体连接部分的宽度是预定的，使得在半导体连接部分的侧壁上的不同量的薄化导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。通过补偿不同晶面的不同稀释速率，可以为不同的晶体取向形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不充分的稀化。

6. 发明授权

US08080456B2 Robust top-down silicon nanowire structure using a conformal nitride 有权
标题翻译：使用保形氮化物的坚固的自顶向下的硅纳米线结构
公开(公告)号：US08080456B2
公开(公告)日：2011-12-20
申请号：US12469304
申请日：2009-05-20
申请人： Tymon Barwicz , Lidija Sekaric , Jeffrey W. Sleight
发明人： Tymon Barwicz , Lidija Sekaric , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： In one exemplary embodiment, a method for fabricating a nanowire product comprising: providing a wafer having a buried oxide (BOX) upper layer in which a well is formed, the wafer further having a nanowire having ends resting on the BOX layer such that the nanowire forms a beam spanning said well; and forming a mask coating on an upper surface of the BOX layer leaving an uncoated window over a center part of said beam over said well and also forming a mask coating around beam intermediate ends between each end of a beam center part and a side wall of said well. In another exemplary embodiment, a nanowire product comprising: a wafer having a buried oxide (BOX) upper layer in which a well having side walls is formed; a nanowire having ends resting on the BOX layer so as to form a beam spanning said well and said side walls; and a hard mask coating on an upper surface of said BOX layer and around intermediate ends of said beam between each side wall of said well and ends of a center part of said beam leaving an uncoated window over a beam center part through which oxidation of said beam center part can take place.
摘要翻译：在一个示例性实施例中，一种用于制造纳米线产品的方法，包括：提供具有其中形成阱的掩埋氧化物（BOX）上层的晶片，所述晶片还具有具有搁置在BOX层上的端部的纳米线，使得纳米线形成横跨所述井的梁; 并且在BOX层的上表面上形成掩模涂层，在所述孔的中心部分上留下未涂覆的窗口，并且还在梁的中心部分的两端和侧壁之间的梁中间端部说得好在另一个示例性实施例中，纳米线产品包括：具有掩埋氧化物（BOX）上层的晶片，其中形成具有侧壁的阱; 具有搁置在BOX层上的端部以形成横跨所述井和所述侧壁的梁的纳米线; 以及在所述BOX层的上表面上并且在所述孔的每个侧壁和所述梁的中心部分的端部之间的所述梁的中间端周围的硬掩模涂层，在光束中心部分上留下未涂覆的窗口，通过所述光束中心部分氧化所述梁中心部分可以发生。

7. 发明授权

US08299565B2 Semiconductor nanowires having mobility-optimized orientations 有权
标题翻译：具有移动性优化取向的半导体纳米线
公开(公告)号：US08299565B2
公开(公告)日：2012-10-30
申请号：US13075551
申请日：2011-03-30
申请人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
发明人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
IPC分类号： H01L29/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , H01L29/0673 , H01L29/125 , H01L29/42392 , H01L29/78696
摘要： Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.
摘要翻译：通过在电介质材料层上的半导体层进行平版印刷图案，形成各自包括半导体连接部分和两个邻接焊盘部分的原型半导体结构。半导体连接部分的侧壁被定向为使第一类型半导体结构的空穴迁移率最大化，并使第二类型半导体结构的电子迁移率最大化。通过半导体结构的氧化来减薄半导体连接部分的宽度，以不同的速率降低不同的晶体取向。半导体连接部分的宽度是预定的，使得在半导体连接部分的侧壁上的不同量的薄化导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。通过补偿不同晶面的不同稀释速率，可以为不同的晶体取向形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不充分变薄。

8. 发明申请

US20100252814A1 SEMICONDUCTOR NANOWIRES HAVING MOBILITY-OPTIMIZED ORIENTATIONS 有权
标题翻译：具有移动优化方位的半导体纳米级
公开(公告)号：US20100252814A1
公开(公告)日：2010-10-07
申请号：US12417796
申请日：2009-04-03
申请人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
发明人： Lidija Sekaric , Tymon Barwicz , Dureseti Chidambarrao
IPC分类号： H01L29/12 , H01L21/782
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , H01L29/0673 , H01L29/125 , H01L29/42392 , H01L29/78696
摘要： Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.
摘要翻译：通过在电介质材料层上的半导体层进行平版印刷图案，形成各自包括半导体连接部分和两个邻接焊盘部分的原型半导体结构。半导体连接部分的侧壁被定向为使第一类型半导体结构的空穴迁移率最大化，并使第二类型半导体结构的电子迁移率最大化。通过半导体结构的氧化来减薄半导体连接部分的宽度，以不同的速率降低不同的晶体取向。半导体连接部分的宽度是预定的，使得在半导体连接部分的侧壁上的不同量的薄化导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。通过补偿不同晶面的不同稀释速率，可以为不同的晶体取向形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不充分变薄。

9. 发明授权

US08445948B2 Gate patterning of nano-channel devices 失效
标题翻译：纳米通道器件的栅极图案化
公开(公告)号：US08445948B2
公开(公告)日：2013-05-21
申请号：US12886139
申请日：2010-09-20
申请人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L29/78
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine-and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译：提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。在另一个实施例中，使用封装/钝化层。在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

10. 发明申请

US20110006367A1 GATE PATTERNING OF NANO-CHANNEL DEVICES 失效
标题翻译： NANO通道设备的门控方案
公开(公告)号：US20110006367A1
公开(公告)日：2011-01-13
申请号：US12886139
申请日：2010-09-20
申请人： Nicholas C.M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C.M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L27/12
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译：提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。在另一个实施例中，使用封装/钝化层。在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

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