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1. 发明授权

US06316311B1 Method of forming borderless contact 失效
标题翻译：形成无边界接触的方法
公开(公告)号：US06316311B1
公开(公告)日：2001-11-13
申请号：US09203036
申请日：1998-12-01
申请人： Tung-Po Chen , Tong-Yu Chen , Keh-Ching Huang , Jacob Chen
发明人： Tung-Po Chen , Tong-Yu Chen , Keh-Ching Huang , Jacob Chen
IPC分类号： H01L218242
CPC分类号： H01L21/76897 , H01L27/10873 , H01L27/10894
摘要： A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the logic region. The MOS transistor comprises a gate, a source/drain region and a cap insulating layer on the gate. An etching stop layer is formed on the substrate to cover the MSO transistor and the STI structure. A dielectric layer is formed in the etching stop layer. The dielectric layer, the etching stop layer and the cap insulating layer are partially removed to form a first opening according to the pattern of a first mask layer. The first opening exposes the gate. According to the pattern of a second mask layer, the dielectric layer and the etching stop layer are partially removed to form openings, which expose the source/drain region, in the dielectric layer.
摘要翻译：提供了形成无边界接触的方法。提供基板。衬底至少具有逻辑区域和存储区域。在逻辑区域上形成MOS晶体管和STI结构。 MOS晶体管包括栅极，源极/漏极区域和栅极上的帽绝缘层。在衬底上形成蚀刻停止层以覆盖MSO晶体管和STI结构。在蚀刻停止层中形成介电层。根据第一掩模层的图案，介电层，蚀刻停止层和盖绝缘层被部分去除以形成第一开口。第一个开放暴露了大门。根据第二掩模层的图案，电介质层和蚀刻停止层被部分地去除以形成在电介质层中暴露源/漏区的开口。

2. 发明授权

US06187674B1 Manufacturing method capable of preventing corrosion and contamination of MOS gate 失效
标题翻译：能够防止MOS栅的腐蚀和污染的制造方法
公开(公告)号：US06187674B1
公开(公告)日：2001-02-13
申请号：US09208605
申请日：1998-12-08
申请人： Tung-Po Chen , Yung-Chang Lin , Keh-Ching Huang , Jacob Chen
发明人： Tung-Po Chen , Yung-Chang Lin , Keh-Ching Huang , Jacob Chen
IPC分类号： H01L2144
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/28247 , H01L29/4941
摘要： A MOS gate manufacturing operation is capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate. The thin oxide layer is capable of protecting the barrier layer against acid corrosion without causing any noticeable increase in gate conductivity.
摘要翻译： MOS门制造操作能够防止酸腐蚀和车站污染。该制造方法包括以下步骤：在硅衬底上顺序地形成多晶硅层，阻挡层，硅化物层和覆盖层，然后蚀刻以形成栅极结构。接下来，进行快速热处理以在阻挡层的暴露的侧壁上形成氧化物层。最后，通过在栅极的每一侧上形成具有轻掺杂漏极结构的源极/漏极区域来清洁衬底。薄氧化物层能够保护阻挡层免受酸腐蚀，而不会导致栅极导电性的任何明显增加。

3. 发明授权

US6060349A Planarization on an embedded dynamic random access memory 失效
标题翻译：嵌入式动态随机存取存储器的平面化
公开(公告)号：US6060349A
公开(公告)日：2000-05-09
申请号：US152449
申请日：1998-09-14
申请人： Tzu-Min Peng , Keh-Ching Huang , Tung-Po Chen , Tz-Guei Jung
发明人： Tzu-Min Peng , Keh-Ching Huang , Tung-Po Chen , Tz-Guei Jung
IPC分类号： H01L21/8242
CPC分类号： H01L27/10844 , H01L27/10852
摘要： A planarization method used in fabricating an embedded dynamic random access memory (DRAM). After a number of metal-oxide semiconductor (MOS) transistors and a number of capacitors are formed on a semiconductor substrate, a first inter-layer di-electric (ILD) layer is formed over the substrate. The embedded DRAM is divided into a memory region and a logic region. Next, planarization is performed. A dummy metal layer is formed and coupled to an interchangeable source/drain region of the MOS transistor in the logic region. Then a second ILD layer is formed over the logic region to compensate difference in height between the logic region and the memory region. Then, a via hole/plug is formed in the logic region to extend the first metal layer. A second metal layer with required contact window/plugs is formed over the substrate.
摘要翻译：用于制造嵌入式动态随机存取存储器（DRAM）的平面化方法。在半导体衬底上形成多个金属氧化物半导体（MOS）晶体管和多个电容器之后，在衬底上形成第一层间二电极（ILD）层。嵌入式DRAM被分成存储区域和逻辑区域。接下来，进行平坦化。形成虚设的金属层并与逻辑区域中的MOS晶体管的可互换的源/漏区耦合。然后在逻辑区域上形成第二ILD层以补偿逻辑区域和存储区域之间的高度差异。然后，在逻辑区域中形成通孔/插头以延伸第一金属层。在衬底上形成具有所需接触窗/插塞的第二金属层。

4. 发明授权

US6133130A Method for fabricating an embedded dynamic random access memory using self-aligned silicide technology 有权
标题翻译：使用自对准硅化物技术制造嵌入式动态随机存取存储器的方法
公开(公告)号：US6133130A
公开(公告)日：2000-10-17
申请号：US181530
申请日：1998-10-28
申请人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
发明人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
IPC分类号： H01L21/285 , H01L21/336 , H01L21/8234 , H01L21/8242 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/10873 , H01L21/28518 , H01L21/823443 , H01L27/10894 , H01L29/665
摘要： A method includes a self-aligned silicide (Salicide) technology in fabrication of an embedded dynamic random access memory (DRAM). On a silicon wafer, a first MOS transistor is formed in a logic device region, and second MOS transistor is formed in a memory device region. The improved method includes forming an insulating layer over the substrate at least covering the first (second) MOS transistor. A top portion of the insulating layer is removed to expose only a top portion of the first (second) gate structure. A portion of the insulating layer covering the first MOS transistor is removed to expose the first MOS transistor. Using the remaining insulating layer on the second MOS transistor as a mask, the Salicide fabrication process is performed to form a self-aligned silicide layer on the first interchangeable source/drain region, and the exposed top surface of the first (second) polysilicon gate structure.
摘要翻译：一种方法包括在嵌入式动态随机存取存储器（DRAM）的制造中的自对准硅化物（Salicide）技术。在硅晶片上，第一MOS晶体管形成在逻辑器件区域中，第二MOS晶体管形成在存储器件区域中。改进的方法包括在衬底上形成至少覆盖第一（第二）MOS晶体管的绝缘层。去除绝缘层的顶部以仅露出第一（第二）栅极结构的顶部。覆盖第一MOS晶体管的绝缘层的一部分被去除以暴露第一MOS晶体管。使用第二MOS晶体管上的剩余绝缘层作为掩模，执行自对准硅化物制造工艺以在第一可互换源极/漏极区上形成自对准硅化物层，并且第一（第二）多晶硅栅极的暴露的顶表面结构体。

5. 发明授权

US06225155B1 Method of forming salicide in embedded dynamic random access memory 失效
标题翻译：嵌入式动态随机存取存储器中形成自杀人的方法
公开(公告)号：US06225155B1
公开(公告)日：2001-05-01
申请号：US09208602
申请日：1998-12-08
申请人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
发明人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
IPC分类号： H01L218234
CPC分类号： H01L27/10894 , H01L21/823814 , H01L21/823835 , H01L27/10873
摘要： In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain region. The insulating layer on a gate and a source/drain region in a logic region and a gate in a memory region. Salicide layers are formed on the three regions mentioned above. Formation of the salicide layers can lower resistance of the three regions, increase speed and can avoid forming a salicide layer on the source/drain region in the memory region. Thus, current leakage can be avoided. In addition, the step of forming a salicide layer is conducted after the annealing process of the source/drain region, so problems of thermal stability and inter-diffusion of impurities in the polysilicon layer can also be solved.
摘要翻译：在嵌入式动态随机存取存储器中形成硅化物层的方法中，在对源极/漏极区域进行退火处理之后，在衬底上顺序地形成薄氧化物层，氮化硅层和厚氧化物层。逻辑区域中的栅极和源极/漏极区域上的绝缘层以及存储区域中的栅极。在上述三个区域上形成硅化物层。自对准层的形成可以降低三个区域的电阻，提高速度，并且可以避免在存储区域的源极/漏极区域上形成自对准硅化物层。因此，可以避免电流泄漏。此外，在源极/漏极区域的退火处理之后进行形成硅化物层的步骤，因此也可以解决多晶硅层中的杂质的热稳定性和相互扩散问题。

6. 发明授权

US06197672B1 Method for forming polycide dual gate 失效
标题翻译：多晶硅双栅极的形成方法
公开(公告)号：US06197672B1
公开(公告)日：2001-03-06
申请号：US09208271
申请日：1998-12-08
申请人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
发明人： Yung-Chang Lin , Tung-Po Chen , Jacob Chen
IPC分类号： H01L213205
CPC分类号： H01L21/28061 , H01L29/4941
摘要： A method for forming a dual polycide gate. A substrate that has an isolation structure is provided, a polysilicon layer (or an &agr;-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a dual gate having an N-type gate and a P-type gate. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a polycide gate, a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.
摘要翻译：一种形成双重多晶硅栅极的方法。提供具有隔离结构的衬底，在衬底上沉积多晶硅层（或α-Si层），将N型和P型掺杂剂注入到多晶硅层中以形成具有N- 型门和P型门。执行退火步骤以恢复多晶硅层的表面晶体结构，在掺杂多晶硅层上沉积氧化物层，并且在氧化物层上形成硅化物层。硅化物层，氧化物层和多晶硅层被定义为形成多晶硅栅极，在衬底的栅极旁边形成轻掺杂的源极/漏极区域。在栅极的侧壁上形成间隔物，并且在衬底中的间隔物旁边形成重掺杂的源/漏区。

7. 发明授权

US06177334B1 Manufacturing method capable of preventing corrosion of metal oxide semiconductor 有权
标题翻译：能够防止金属氧化物半导体的腐蚀的制造方法
公开(公告)号：US06177334B1
公开(公告)日：2001-01-23
申请号：US09203024
申请日：1998-12-01
申请人： Tung-Po Chen , Yung-Chang Lin , Jacob Chen
发明人： Tung-Po Chen , Yung-Chang Lin , Jacob Chen
IPC分类号： H01L2120
CPC分类号： H01L21/02071 , H01L21/28061 , H01L21/28247 , H01L21/32137 , H01L29/6659
摘要： A manufacturing method is capable of preventing corrosion of a metal oxide semiconductor. The manufacturing method sequentially forms a polysilicon layer, a silicide layer and a top cap layer over a substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the silicide layer. Finally, the substrate is cleaned, and then of a source/drain region having a lightly doped drain structure is formed on each side of the gate.
摘要翻译：制造方法能够防止金属氧化物半导体的腐蚀。制造方法在衬底上顺序地形成多晶硅层，硅化物层和顶盖层，然后蚀刻以形成栅极结构。接下来，进行快速热处理以在硅化物层的暴露的侧壁上形成氧化物层。最后，清洗衬底，然后在栅极的每一侧形成具有轻掺杂漏极结构的源/漏区。

8. 发明授权

US07074674B1 Method for manufacturing one-time electrically programmable read only memory 失效
标题翻译：制造一次电可编程只读存储器的方法
公开(公告)号：US07074674B1
公开(公告)日：2006-07-11
申请号：US11160176
申请日：2005-06-13
申请人： Ko-Hsing Chang , Tung-Po Chen , Tung-Ming Lai , Chen-Chiu Hsue
发明人： Ko-Hsing Chang , Tung-Po Chen , Tung-Ming Lai , Chen-Chiu Hsue
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/7833
摘要： A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined to form the floating gate is exposed and then a cap layer is formed thereon. The first patterned mask layer is removed and then a second conductive layer and a second patterned mask layer are formed over the substrate. A word line and a floating gate are formed using the second patterned mask layer and the cap layer as a mask. The second patterned mask layer is removed and then source/drain regions are formed in the substrate on both sides of the word line and the floating gate and between the word line and the floating gate.
摘要翻译：描述了用于制造OTEPROM的方法。在衬底上形成隧道氧化物层，第一导电层，第一图案化掩模层。在衬底中形成沟槽。形成绝缘层以填充沟槽。目的地形成浮栅的第一导电层的一部分被暴露，然后在其上形成覆盖层。去除第一图案化掩模层，然后在衬底上形成第二导电层和第二图案化掩模层。使用第二图案化掩模层和盖层作为掩模形成字线和浮栅。去除第二图案化掩模层，然后在字线和浮栅两侧以及字线和浮栅之间的衬底中形成源极/漏极区。

9. 发明授权

US6156633A Process for forming high temperature stable self-aligned metal silicide layer 失效
标题翻译：形成高温稳定自对准金属硅化物层的工艺
公开(公告)号：US6156633A
公开(公告)日：2000-12-05
申请号：US34261
申请日：1998-03-04
申请人： Hong-Tsz Pan , Tung-Po Chen
发明人： Hong-Tsz Pan , Tung-Po Chen
IPC分类号： H01L21/285 , H01L21/44
CPC分类号： H01L21/28518
摘要： A process for forming high temperature stable self-aligned silicide layer that not only establishes itself smoothly and uniformly despite the use of a high temperature in the siliciding reaction, but also can withstand other subsequent high temperature thermal processing operations and maintaining a stable metal silicide layer profile thereafter. Moreover, desired thickness and uniformity of the metal silicide layer can be obtained by suitably adjusting the amorphous implant parameters, while the use of a titanium nitride cap layer help to stabilize the metal silicide layer during high temperature formation and that a stable and uniform metal silicide layer profile can be ensured even if subsequent high temperature processing operations are performed.
摘要翻译：用于形成高温稳定的自对准硅化物层的方法，其不仅在硅化反应中使用高温使其自身平滑均匀，而且还可以承受其它随后的高温热处理操作并保持稳定的金属硅化物层之后的档案。而且，通过适当地调整非晶态注入参数，可以获得所需的金属硅化物层的厚度和均匀性，而使用氮化钛盖层有助于在高温形成期间稳定金属硅化物层，并且使金属硅化物稳定且均匀即使执行后续的高温处理操作，也可以确保层的轮廓。

10. 发明授权

US6156126A Method for reducing or avoiding the formation of a silicon recess in SDE junction regions 有权
标题翻译：用于减少或避免在SDE连接区域中形成硅凹槽的方法
公开(公告)号：US6156126A
公开(公告)日：2000-12-05
申请号：US484790
申请日：2000-01-18
申请人： Tung-Po Chen , Jih-Wen Chou
发明人： Tung-Po Chen , Jih-Wen Chou
IPC分类号： G03F7/42 , H01L21/265 , H01L21/306 , H01L21/336 , B08B3/04
CPC分类号： H01L21/02052 , H01L21/26513 , H01L29/6659 , G03F7/422 , Y10S134/902
摘要： A method for cleaning a silicon wafer. The method includes intentionally exposing the wafer into a volatile solvent with a polarity between about 2 and 4, whereby the wafer is cleaned by the solvent such that the formation of silicon recesses in source/drain extension regions on the silicon wafer can be prevented or avoided.
摘要翻译：一种清洗硅晶片的方法。该方法包括将晶片有意地暴露在极性为约2和4之间的挥发性溶剂中，由此通过溶剂清洁晶片，从而可以防止或避免在硅晶片上的源极/漏极延伸区域中形成硅凹槽。

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