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1. 发明申请

US20060284234A1 Structure of a non-volatile memory device and operation method 审中-公开
标题翻译：非易失性存储器件的结构和操作方法
公开(公告)号：US20060284234A1
公开(公告)日：2006-12-21
申请号：US11154378
申请日：2005-06-15
申请人： Tsung-Min Hsieh , Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Tsung-Min Hsieh , Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile memory device, including composite gate structures formed on a substrate in series along a bit line (BL) direction. Each of the composite gate structures has a first storage gate, a second storage gate, and a selection gate between the two storage gates. Each of the composite gate structures is respectively coupled to two world line (WL) connection terminals at the two storage gates and a selection terminal at the selection gate. Each of the storage gates corresponds to a memory bit cell. Multiple doped regions are in the substrate between the composite gate structures. A first selection doped region are formed in the substrate and coupled between a BL connection terminal and a first edge one of the composite gate structure. A second selection doped region is formed in the substrate and coupled between a second edge one of the composite gate structures and a voltage terminal.
摘要翻译：一种非易失性存储器件，包括沿着位线（BL）方向串联形成在衬底上的复合栅极结构。复合栅极结构中的每一个在两个存储栅极之间具有第一存储栅极，第二存储栅极和选择栅极。复合栅极结构中的每一个分别耦合到两个存储栅极处的两个世界线（WL）连接端子和选择栅极处的选择端子。每个存储门对应于存储器位单元。多个掺杂区域在复合栅极结构之间的衬底中。第一选择掺杂区域形成在衬底中并且耦合在BL连接端子和复合栅极结构中的第一边缘之间。第二选择掺杂区域形成在衬底中并且耦合在复合栅极结构之一的第二边缘和电压端子之间。

2. 发明申请

US20060086967A1 Nonvolatile memory device and method for fabricating the same 有权
公开(公告)号：US20060086967A1
公开(公告)日：2006-04-27
申请号：US11297266
申请日：2005-12-07
申请人： Tsung-Min Hsieh , Jhyy-Cheng Liou , Chien-Hsing Lee , Chin-Hsi Lin
发明人： Tsung-Min Hsieh , Jhyy-Cheng Liou , Chien-Hsing Lee , Chin-Hsi Lin
IPC分类号： G11C11/22
CPC分类号： G11C16/0491 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.

3. 发明申请

US20060284240A1 Structure of a non-volatile memory device and operation method 审中-公开
标题翻译：非易失性存储器件的结构和操作方法
公开(公告)号：US20060284240A1
公开(公告)日：2006-12-21
申请号：US11473578
申请日：2006-06-22
申请人： Tsung-Min Hsieh , Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Tsung-Min Hsieh , Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile memory device includes composite gate structures formed on a substrate in series along a bit line direction. The composite gate structure has a first storage gate structure, a second storage gate structure, and a selection gate between the two storage gate structures. Each of the composite gate structures is respectively coupled to two world line connection terminals at the two storage gate structures and a selection terminal at the selection gate. Each of the storage gate structures corresponds to a memory bit cell. Multiple doped regions are in the substrate between the composite gate structures. A first selection doped region are formed in the substrate and coupled between a BL connection terminal and a first edge one of the composite gate structure. A second selection doped region is formed in the substrate and coupled between a second edge one of the composite gate structures and a voltage terminal.
摘要翻译：非易失性存储器件包括沿着位线方向串联地形成在衬底上的复合栅极结构。复合栅极结构具有第一存储栅极结构，第二存储栅极结构和两个存储栅极结构之间的选择栅极。复合栅极结构中的每一个分别耦合到两个存储栅极结构处的两个世界线连接端子和选择栅极处的选择端子。每个存储门结构对应于存储器位单元。多个掺杂区域在复合栅极结构之间的衬底中。第一选择掺杂区域形成在衬底中并且耦合在BL连接端子和复合栅极结构中的第一边缘之间。第二选择掺杂区域形成在衬底中并且耦合在复合栅极结构之一的第二边缘和电压端子之间。

4. 发明授权

US07119394B2 Nonvolatile memory device and method for fabricating the same 有权
公开(公告)号：US07119394B2
公开(公告)日：2006-10-10
申请号：US11297266
申请日：2005-12-07
申请人： Tsung-Min Hsieh , Jhyy-Cheng Liou , Chien-Hsing Lee , Chin-Hsi Lin
发明人： Tsung-Min Hsieh , Jhyy-Cheng Liou , Chien-Hsing Lee , Chin-Hsi Lin
IPC分类号： H01L29/788
CPC分类号： G11C16/0491 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.

5. 发明授权

US07020018B2 Nonvolatile memory device and method for fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07020018B2
公开(公告)日：2006-03-28
申请号：US10987045
申请日：2004-11-12
申请人： Tsung-Min Hsieh , Jhyy-Cheng Liou , Chien-Hsing Lee , Chin-Hsi Lin
发明人： Tsung-Min Hsieh , Jhyy-Cheng Liou , Chien-Hsing Lee , Chin-Hsi Lin
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.
摘要翻译：非易失性存储器的结构在衬底中具有沿着第一方向延伸的多个掩埋位线。选择栅极结构线位于掩埋位线之间。在用作电荷存储区域的选择栅极结构线的两侧上的多个堆叠电介质膜不延伸到位线，并且电介质层与基板的与堆叠的电介质膜相邻的表面接触。字线在衬底上方，其中堆叠的电介质膜和电介质层插入在除了选择栅极结构线之外的区域之间的WL和衬底之间，沿着不同于第一方向的第二方向延伸。由于电荷存储层不完全覆盖在选择栅极结构线和位线之间，所以形成附加的控制栅极。

6. 发明申请

US20050237777A1 Nonvolatile memory device and method for fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20050237777A1
公开(公告)日：2005-10-27
申请号：US10987045
申请日：2004-11-12
申请人： Tsung-Min Hsieh , Jhyy-Cheng Liou , Chien-Hsing Lee , Chin-Hsi Lin
发明人： Tsung-Min Hsieh , Jhyy-Cheng Liou , Chien-Hsing Lee , Chin-Hsi Lin
IPC分类号： G11C16/04 , H01L21/8246 , H01L27/115
CPC分类号： G11C16/0491 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.
摘要翻译：非易失性存储器的结构在衬底中具有沿着第一方向延伸的多个掩埋位线。选择栅极结构线位于掩埋位线之间。在用作电荷存储区域的选择栅极结构线的两侧上的多个堆叠电介质膜不延伸到位线，并且电介质层与基板的与堆叠的电介质膜相邻的表面接触。字线在衬底上方，其中堆叠的电介质膜和电介质层插入在除了选择栅极结构线之外的区域之间的WL和衬底之间，沿着不同于第一方向的第二方向延伸。由于电荷存储层不完全覆盖在选择栅极结构线和位线之间，所以形成附加的控制栅极。

7. 发明授权

US07061042B2 Double-cell memory device 有权
标题翻译：双电池存储器件
公开(公告)号：US07061042B2
公开(公告)日：2006-06-13
申请号：US10871170
申请日：2004-06-18
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7923
摘要： A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.
摘要翻译：存储器阵列器件具有多个栅极结构线，沿着一个方向相邻地设置在衬底上，其中栅极结构线的至少一部分具有记忆功能。多个第一掺杂区域，在栅极结构线的第一条线的一侧的衬底中。在栅极结构线的最后一行的一侧的衬底中的多个第二掺杂区域。其中第一掺杂区和第二掺杂区相对于多个位线分别用于多对掺杂区。换句话说，每个存储单元的常规源/漏区被保存。相反，栅极线相邻地放置在一起。

8. 发明申请

US20060007724A1 Double-cell memory device 审中-公开
公开(公告)号：US20060007724A1
公开(公告)日：2006-01-12
申请号：US11222377
申请日：2005-09-07
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C17/00
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7923
摘要： A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.

9. 发明申请

US20050224865A1 CIRCUIT LAYOUT AND STRUCTURE FOR A NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的电路布局和结构
公开(公告)号：US20050224865A1
公开(公告)日：2005-10-13
申请号：US10823488
申请日：2004-04-12
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C11/34 , G11C16/04 , H01L21/8246 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0491 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/42328 , H01L29/42344 , H01L29/7887 , H01L29/7923
摘要： A structure of non-volatile memory contains a substrate. A plurality of bit lines are formed in the substrate along a first direction, wherein each of the bit lines also serve as a source/drain (S/D) region. A first dielectric layer is disposed over the substrate. A plurality of selection gate (SG) lines are formed over the first dielectric layer between the bit lines. A plurality of charge-storage structure layer are formed over the substrate between the bit lines and the SG lines. A second dielectric layer is formed over the SG lines and a third dielectric layer is formed over the bit lines. A plurality of word lines are formed over the substrate along a second direction, which is crossing the first direction for the bit lines. Wherein, when a selected one of the SG lines is applied a voltage, another S/D region is created in the substrate under the selected one of the SG lines.
摘要翻译：非易失性存储器的结构包含衬底。沿着第一方向在衬底中形成多个位线，其中每个位线还用作源极/漏极（S / D）区域。第一电介质层设置在衬底上。在位线之间的第一电介质层上形成多个选择栅（SG）线。在位线和SG线之间的衬底上形成多个电荷存储结构层。在SG线上形成第二电介质层，并且在位线之上形成第三介电层。沿着与位线的第一方向交叉的第二方向在基板上形成多个字线。其中，当所选择的一条SG线施加电压时，在所选择的一条SG线之下的衬底中产生另一S / D区。

10. 发明申请

US20050170588A1 Method for forming multi-level mask ROM cell and NAND multi-level mask ROM 有权
标题翻译：用于形成多电平掩模ROM单元和NAND多级掩模ROM的方法
公开(公告)号：US20050170588A1
公开(公告)日：2005-08-04
申请号：US10886981
申请日：2004-07-07
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C11/56 , H01L21/8234 , H01L21/8246 , H01L27/112
CPC分类号： G11C11/5692 , G11C16/0483 , H01L27/112 , H01L27/1122 , H01L27/1126
摘要： The present invention relates to a multi-level read only memory cell that can store two bits and the fabrication method thereof. The multi-level ROM cell has the storage capacity of two bits and the resultant NAND type ROM memory array can provide four logic states of two bits, thus increasing the data storage capacity.
摘要翻译：本发明涉及可存储两位的多级只读存储器单元及其制造方法。多级ROM单元具有两位的存储容量，并且所得的NAND型ROM存储器阵列可以提供两位的四个逻辑状态，从而增加数据存储容量。

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