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1. 发明授权

US08488866B2 Method of inspecting mask pattern and mask pattern inspection apparatus 有权
标题翻译：检查掩模图案和掩模图案检查装置的方法
公开(公告)号：US08488866B2
公开(公告)日：2013-07-16
申请号：US12708041
申请日：2010-02-18
申请人： Tsuneo Terasawa , Toshihiko Tanaka , Hiroyuki Shigemura , Hajime Aoyama , Osamu Suga
发明人： Tsuneo Terasawa , Toshihiko Tanaka , Hiroyuki Shigemura , Hajime Aoyama , Osamu Suga
IPC分类号： G06K9/00
CPC分类号： G01N21/9501 , B82Y10/00 , B82Y40/00 , G01N21/956 , G03F1/24 , G03F1/84 , G03F7/70941 , G06T7/0006 , G06T2207/30148
摘要： A inspection image data of the chip A is captured and the data representing the amount of correction of flare corresponded to the chip A is appropriately loaded from the map storage block. Next, a inspection image of the chip A′ is captured, and the data representing the amount of correction of flare corresponded to the chip A′ is loaded from the flare map storage block as the amount of shifting of the edge of the contour of the pattern. The amount of correction is converted, by a correction data generation block which is a correction data generator, into the amount of geometrical correction of pattern which provides correction data. In the comparison block, the images of the geometry of two chips are compared and corrected on the amount of correction of flare generated by a correction data generation block, to thereby judge whether defect is found or not.
摘要翻译：捕获芯片A的检查图像数据，并且从地图存储块适当地加载表示对应于芯片A的闪光的校正量的数据。接下来，捕获芯片A'的检查图像，并且表示与芯片A'相对应的闪光量的校正量的数据从闪光图存储块加载为轮廓的边缘的移位量模式。通过作为校正数据生成器的校正数据生成块将修正量转换为提供校正数据的图案的几何校正量。在比较块中，对由校正数据生成块生成的闪光的校正量进行比较和修正两个芯片的几何图像，从而判断是否存在缺陷。

2. 发明申请

US20070074146A1 Method for designing mask pattern and method for manufacturing semiconductor device 审中-公开
标题翻译：设计掩模图案的方法和制造半导体器件的方法
公开(公告)号：US20070074146A1
公开(公告)日：2007-03-29
申请号：US11526783
申请日：2006-09-26
申请人： Toshihiko Tanaka , Osamu Suga , Tsuneo Terasawa , Tetsuya Higuchi , Hidenori Sakanashi , Hirokazu Nosato , Tetsuaki Matsunawa
发明人： Toshihiko Tanaka , Osamu Suga , Tsuneo Terasawa , Tetsuya Higuchi , Hidenori Sakanashi , Hirokazu Nosato , Tetsuaki Matsunawa
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A semiconductor chip is manufactured using a cell library pattern obtained by performing OPC (optical proximity correction) process at the time of a cell single arrangement to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance. A plurality of cell libraries are arranged to design a mask pattern and a correction amount of OPC performed to the cell libraries is changed with taking into account the influence of a pattern of cell libraries arranged around a target cell. Further, a cell group with the same arrangement of surrounding cells including the target cell is extracted and is registered as a cell set, and a cell set with the same cell arrangement as that of the registered cell set is produced by copying without re-calculating OPC inside the cell set.
摘要翻译：使用通过在单元格单元配置时对预先形成半导体电路图案的基本结构的单元库图案执行OPC（光学邻近校正）处理而获得的单元库模式来制造半导体芯片。布置多个单元库以设计掩模图案，并且考虑到布置在目标单元周围的单元库的图案的影响，改变对单元库执行的OPC的校正量。此外，提取具有包括目标单元的周围单元的相同排列的单元组，并将其注册为单元组，并且通过复制产生具有与注册单元组相同单元布置的单元组，而不重新计算 OPC内部的单元格集。

3. 发明授权

US09063098B2 Method of inspecting mask, mask inspection device, and method of manufacturing mask 有权
标题翻译：掩模检查方法，掩模检查装置以及制造掩模的方法
公开(公告)号：US09063098B2
公开(公告)日：2015-06-23
申请号：US13549482
申请日：2012-07-15
申请人： Tsuneo Terasawa , Osamu Suga
发明人： Tsuneo Terasawa , Osamu Suga
IPC分类号： G03F1/84 , G01N21/88 , G01N21/956
CPC分类号： G03F1/22 , G01N21/8806 , G01N21/95 , G01N21/956 , G01N2021/8822 , G01N2021/95676 , G01N2201/061 , G03F1/84
摘要： There is provided a method of high-sensitively detecting both of a phase defect existing in a mask blank and a phase defect remaining after manufacturing an EUVL mask. When the mask blank is inspected, EUV light having illumination NA to be within an inner NA but a larger value is irradiated. When the EUVL mask is inspected, by using a dark-field imaging optical system including a center shielding portion for shielding EUV light and a linear shielding portion for shielding the EUV light whose width is smaller than a diameter of the center shielding portion, the center shielding portion and the linear shielding portion being included in a pupil plane, the EUV light having illumination NA as large as or smaller than the width of the linear shielding portion is irradiated.
摘要翻译：提供了一种高灵敏度地检测存在于掩模坯料中的相位缺陷和在制造EUVL掩模之后剩余的相缺陷的方法。当检查掩模毛坯时，照射具有NA内但NA值越大的EUV光。当检查EUVL掩模时，通过使用包括用于屏蔽EUV光的中心屏蔽部分和用于屏蔽宽度小于中心屏蔽部分的直径的EUV光的线性屏蔽部分的暗视场成像光学系统，中心屏蔽部分和线性屏蔽部分包括在光瞳平面中，照射具有大于或等于线状屏蔽部分的宽度的照明NA的EUV光。

4. 发明申请

US20130017475A1 METHOD OF INSPECTING MASK, MASK INSPECTION DEVICE, AND METHOD OF MANUFACTURING MASK 有权
公开(公告)号：US20130017475A1
公开(公告)日：2013-01-17
申请号：US13549482
申请日：2012-07-15
申请人： Tsuneo TERASAWA , Osamu Suga
发明人： Tsuneo TERASAWA , Osamu Suga
IPC分类号： G03F1/22 , G01N21/95
CPC分类号： G03F1/22 , G01N21/8806 , G01N21/95 , G01N21/956 , G01N2021/8822 , G01N2021/95676 , G01N2201/061 , G03F1/84
摘要： There is provided a method of high-sensitively detecting both of a phase defect existing in a mask blank and a phase defect remaining after manufacturing an EUVL mask. When the mask blank is inspected, EUV light having illumination NA to be within an inner NA but a larger value is irradiated. When the EUVL mask is inspected, by using a dark-field imaging optical system including a center shielding portion for shielding EUV light and a linear shielding portion for shielding the EUV light whose width is smaller than a diameter of the center shielding portion, the center shielding portion and the linear shielding portion being included in a pupil plane, the EUV light having illumination NA as large as or smaller than the width of the linear shielding portion is irradiated.

5. 发明申请

US20090148781A1 REFLECTIVE-TYPE MASK 有权
标题翻译：反射型面膜
公开(公告)号：US20090148781A1
公开(公告)日：2009-06-11
申请号：US12329126
申请日：2008-12-05
申请人： Takashi KAMO , Osamu Suga , Toshihiko Tanaka
发明人： Takashi KAMO , Osamu Suga , Toshihiko Tanaka
IPC分类号： G03F1/00
CPC分类号： G03F1/24 , B82Y10/00 , B82Y40/00 , G03F1/58
摘要： A reflective-type mask having a main surface including a pattern region in the main surface, the pattern region including a multilayer reflective film which reflects the exposure light and a first absorber pattern on the multilayer reflective film, the first absorber pattern including a pattern which absorbs the exposure light and corresponds to a pattern to be formed on a wafer, a light shielding region in the main surface for preventing a region on the wafer excluding a predetermined region from being irradiated with the exposure light when the main surface is irradiated with the exposure light for transferring the first absorber pattern to the predetermined region, the light shielding region including a second absorber pattern having a lower reflectivity to the exposure light than the first absorber pattern and being provided in a position differing from a position in which the first absorber pattern is provided.
摘要翻译：一种反射型掩模，其具有包括主表面中的图案区域的主表面，所述图案区域包括反射所述曝光光的多层反射膜和所述多层反射膜上的第一吸收体图案，所述第一吸收体图案包括图案，吸收曝光光，并且对应于要在晶片上形成的图案，主表面上的遮光区域，用于防止当主表面被照射时，除了预定区域之外的晶片上的区域被照射曝光用于将第一吸收体图案转印到预定区域的曝光光，所述遮光区域包括与所述第一吸收体图案相比对所述曝光光具有较低反射率的第二吸收体图案，并且设置在与所述第一吸收体提供图案。

6. 发明授权

US07960076B2 Reflective-type mask 有权
标题翻译：反光型面膜
公开(公告)号：US07960076B2
公开(公告)日：2011-06-14
申请号：US12329126
申请日：2008-12-05
申请人： Takashi Kamo , Osamu Suga , Toshihiko Tanaka
发明人： Takashi Kamo , Osamu Suga , Toshihiko Tanaka
IPC分类号： G03F1/00
CPC分类号： G03F1/24 , B82Y10/00 , B82Y40/00 , G03F1/58
摘要： A reflective-type mask having a main surface including a pattern region in the main surface, the pattern region including a multilayer reflective film which reflects the exposure light and a first absorber pattern on the multilayer reflective film, the first absorber pattern including a pattern which absorbs the exposure light and corresponds to a pattern to be formed on a wafer, a light shielding region in the main surface for preventing a region on the wafer excluding a predetermined region from being irradiated with the exposure light when the main surface is irradiated with the exposure light for transferring the first absorber pattern to the predetermined region, the light shielding region including a second absorber pattern having a lower reflectivity to the exposure light than the first absorber pattern and being provided in a position differing from a position in which the first absorber pattern is provided.
摘要翻译：一种反射型掩模，其具有包括主表面中的图案区域的主表面，所述图案区域包括反射所述曝光光的多层反射膜和所述多层反射膜上的第一吸收体图案，所述第一吸收体图案包括图案，吸收曝光光并且对应于要在晶片上形成的图案，主表面上的遮光区域，用于防止当主表面被照射时，除了预定区域之外的晶片上的区域被照射曝光用于将第一吸收体图案转印到预定区域的曝光光，所述遮光区域包括与所述第一吸收体图案相比对所述曝光光具有较低反射率的第二吸收体图案，并且设置在与所述第一吸收体提供图案。

7. 发明申请

US20110020737A1 REFLECTION-TYPE EXPOSURE MASK AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：反射型曝光掩模和制造半导体器件的方法
公开(公告)号：US20110020737A1
公开(公告)日：2011-01-27
申请号：US12749250
申请日：2010-03-29
申请人： Takashi Kamo , Osamu Suga
发明人： Takashi Kamo , Osamu Suga
IPC分类号： G03F1/00 , G03F7/20
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/26 , G03F7/70283
摘要： A reflection-type exposure mask includes a multilayer reflective film in a main surface and serving as a high reflective region to an exposure light, and an absorber pattern on the multilayer reflective film and serving as a low reflective region to the exposure light, wherein a phase difference between reflection lights of the exposure light from the multilayer reflective film and the absorber pattern is in a range of 180°±10°, and the absorber pattern includes first and second linear patterns having longitudinal directions intersecting at right angles, contrast values of optical images of the first and second linear patterns formed on a wafer is to be 0.6 or more when one of the longitudinal directions of the first and second patterns agree with an incident direction of the exposure light to the main surface viewed from above the main surface.
摘要翻译：反射型曝光掩模包括主表面中的多层反射膜并且用作曝光用光的高反射区域，并且在多层反射膜上形成作为曝光用光的低反射区域的吸收体图案，其中，来自多层反射膜的曝光光的反射光和吸收体图案之间的相位差在180°±10°的范围内，吸收体图案包括纵向相交成直角的第一和第二线状图案，对比度值形成在晶片上的第一和第二线状图案的光学图像在第一和第二图案的纵向方向之一与主表面上方观察到的曝光的入射方向一致时为0.6以上。

8. 发明授权

US5424173A Electron beam lithography system and method 失效
公开(公告)号：US5424173A
公开(公告)日：1995-06-13
申请号：US158820
申请日：1993-11-26
申请人： Hiroaki Wakabayashi , Osamu Suga , Yoshinori Nakayama , Shinji Okazaki
发明人： Hiroaki Wakabayashi , Osamu Suga , Yoshinori Nakayama , Shinji Okazaki
IPC分类号： H01L21/027 , H01J37/317 , G03F7/20
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3174 , H01J2237/0453 , H01J2237/31769 , H01J2237/31776 , Y10S430/143
摘要： A system and method are provided for compensating for proximity effects between selected adjacent portions of pattern elements on an integrated circuit wafer where it is determined by simulation that undesirable resist patterns will result. The subject lithography system includes projecting an electron beam onto the wafer through an aperture plate of pattern elements to obtain the desired beam pattern. An aperture mask includes a plurality of first portions corresponding to first wafer circuit element portions spaced for avoiding proximity effects on the wafer and a plurality of second portions corresponding to second element portions spaced for obtaining proximity effects between elements on the wafer. The plurality of second portions are sized to have an increased adjacent spacing relative to a resultant adjacent spacing of the corresponding second element portions whereby the resultant adjacent spacing of the second element portions on the wafer is selectively reduced by the proximity effects. Alternatively, or in addition, a wire mesh is provided at the second portions of the aperture plate to reduce the beam intensity for corresponding reduction of the proximity effects.

9. 发明授权

US5097138A Electron beam lithography system and method 失效
标题翻译：电子束光刻系统及方法
公开(公告)号：US5097138A
公开(公告)日：1992-03-17
申请号：US563441
申请日：1990-08-07
申请人： Hiroaki Wakabayashi , Osamu Suga , Yoshinori Nakayama , Shinji Okazaki
发明人： Hiroaki Wakabayashi , Osamu Suga , Yoshinori Nakayama , Shinji Okazaki
IPC分类号： H01L21/027 , H01J37/317
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3174 , H01J2237/0453 , H01J2237/31769 , H01J2237/31776 , Y10S430/143
摘要： A system and method are provided for compensating for proximity effects between selected adjacent portions of pattern elements on an integrated circuit wafer where it is determined by simulation that undesirable resist patterns will result. The subject lithography system includes projecting an electron beam onto the wafer through an aperture plate of pattern elements to obtain the desired beam pattern. An aperture mask includes a plurality of first portions corresponding to first wafer circuit element portions spaced for avoiding proximity effects on the wafer and a plurality of second portions corresponding to second element portions spaced for obtaining proximity effects between elements on the wafer. The plurality of second portions are sized to have an increased adjacent spacing relative to a resultant adjacent spacing of the corresponding second element portions whereby the resultant adjacent spacing of the second element portions on the wafer is selectively reduced by the proximity effects. Alternatively, or in addition, a wire mesh is provided at the second portions of the aperture plate to reduce the beam intensity for corresponding reduction of the proximity effects.
摘要翻译：提供了一种用于补偿集成电路晶片上的图案元件的选定相邻部分之间的接近效应的系统和方法，其中通过模拟确定将导致不期望的抗蚀剂图案。目标光刻系统包括通过图案元件的孔板将电子束投影到晶片上，以获得期望的光束图案。孔径掩模包括对应于间隔开的第一晶片电路元件部分的多个第一部分，以避免对晶片的接近效应，以及对应于间隔开的第二元件部分的多个第二部分，以获得晶片上元件之间的接近效应。多个第二部分的大小相对于相应的第二元件部分的相邻相邻间隔具有增加的相邻间隔，由此通过邻近效应选择性地减小晶片上的第二元件部分的相邻间隔。或者，或另外，在孔板的第二部分处设置金属丝网以减小光束强度，以便相应地减小邻近效应。

10. 发明授权

US08173332B2 Reflection-type exposure mask and method of manufacturing a semiconductor device 有权
标题翻译：反射式曝光掩模和半导体器件的制造方法
公开(公告)号：US08173332B2
公开(公告)日：2012-05-08
申请号：US12749250
申请日：2010-03-29
申请人： Takashi Kamo , Osamu Suga
发明人： Takashi Kamo , Osamu Suga
IPC分类号： G03F1/00
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/26 , G03F7/70283
摘要： A reflection-type exposure mask includes a multilayer reflective film in a main surface and serving as a high reflective region to an exposure light, and an absorber pattern on the multilayer reflective film and serving as a low reflective region to the exposure light, wherein a phase difference between reflection lights of the exposure light from the multilayer reflective film and the absorber pattern is in a range of 180°±10°, and the absorber pattern includes first and second linear patterns having longitudinal directions intersecting at right angles, contrast values of optical images of the first and second linear patterns formed on a wafer is to be 0.6 or more when one of the longitudinal directions of the first and second patterns agree with an incident direction of the exposure light to the main surface viewed from above the main surface.
摘要翻译：反射型曝光掩模包括主表面中的多层反射膜并且用作曝光用光的高反射区域，并且在多层反射膜上形成作为曝光用光的低反射区域的吸收体图案，其中，来自多层反射膜的曝光光的反射光和吸收体图案之间的相位差在180°±10°的范围内，吸收体图案包括纵向相交成直角的第一和第二线状图案，对比度值形成在晶片上的第一和第二线状图案的光学图像在第一和第二图案的纵向方向之一与主表面上方观察到的曝光的入射方向一致时为0.6以上。

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