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    • 5. 发明申请
    • Semiconductor device having universal logic cell
    • 具有通用逻辑单元的半导体器件
    • US20050218936A1
    • 2005-10-06
    • US11092943
    • 2005-03-30
    • Masaharu MizunoKazuhiro Nakajima
    • Masaharu MizunoKazuhiro Nakajima
    • H01L21/822H01L27/04H03K19/173H03K19/0175
    • H03K19/173
    • A universal logic module includes: a first inverter outputting an inverted input signal to an output terminal through a first transfer gate, the inverted input signal having an inverted level of an input signal provided from a first input terminal; and a second inverter outputting an inverted logic signal to the output terminal through a second transfer gate, the inverted logic signal having an inverted level of a first logic signal. The first input terminal is connected to one of a power supply line and a ground line. An input of the first transfer gate is directly connected to the other of the power supply line and the ground line. The first and the second transfer gates are complementarily turned on/off according to a level of a second logic signal. A result of a logical operation between the first and the second logic signals is outputted from the output terminal.
    • 通用逻辑模块包括:第一反相器,通过第一传输门将反相输入信号输出到输出端,反相输入信号具有从第一输入端提供的输入信号的反相电平; 以及第二反相器,通过第二传输门将输出反相逻辑信号输出到输出端,反相逻辑信号具有第一逻辑信号的反相电平。 第一输入端子连接到电源线和接地线之一。 第一传输门的输入直接连接到电源线和接地线中的另一个。 根据第二逻辑信号的电平,第一和第二传输门互补地导通/截止。 从输出端子输出第一和第二逻辑信号之间的逻辑运算的结果。
    • 6. 发明授权
    • Universal logic module and ASIC using the same
    • 通用逻辑模块和ASIC使用相同
    • US06946875B2
    • 2005-09-20
    • US10325572
    • 2002-12-19
    • Kenji YamamotoMasaharu MizunoKazuhiro Nakajima
    • Kenji YamamotoMasaharu MizunoKazuhiro Nakajima
    • H01L21/82H03K19/00H03K19/173H03K19/094
    • H03K19/1735
    • A universal logic module that may have a reduced off-leak current in universal logic cells (100) not used as logic circuits has been disclosed. A universal logic module may include universal logic cells (100) that may be formed with a second wiring for connecting universal logic cells (100) from a base configuration formed with a first wiring. Unused universal logic cell (100) may include transistors in basic cells (A to E) that are non-connected to a power supply (VDD) and/or a ground potential (VSS). Furthermore, unused universal logic cell (100) may include transistors in basic cells (A to E) that may provide a capacitor between a power supply (VDD) and a ground potential (VSS). In this way, off-leak current may be reduced and noise on a power line and/or a ground line may be reduced.
    • 已经公开了可以在不用作逻辑电路的通用逻辑单元(100)中具有减小的漏电流的通用逻辑模块。 通用逻辑模块可以包括可以形成有第二布线的通用逻辑单元(100),用于将通用逻辑单元(100)与形成有第一布线的基座配置相连接。 未使用的通用逻辑单元(100)可以包括未连接到电源(VDD)和/或接地电位(VSS)的基本单元(A至E)中的晶体管。 此外,未使用的通用逻辑单元(100)可以包括可在电源(VDD)和接地电位(VSS)之间提供电容器的基本单元(A至E)中的晶体管。 以这种方式,可以减少泄漏电流,并且可以减少电力线和/或接地线上的噪声。