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    • 1. 发明授权
    • Universal logic module and ASIC using the same
    • 通用逻辑模块和ASIC使用相同
    • US06946875B2
    • 2005-09-20
    • US10325572
    • 2002-12-19
    • Kenji YamamotoMasaharu MizunoKazuhiro Nakajima
    • Kenji YamamotoMasaharu MizunoKazuhiro Nakajima
    • H01L21/82H03K19/00H03K19/173H03K19/094
    • H03K19/1735
    • A universal logic module that may have a reduced off-leak current in universal logic cells (100) not used as logic circuits has been disclosed. A universal logic module may include universal logic cells (100) that may be formed with a second wiring for connecting universal logic cells (100) from a base configuration formed with a first wiring. Unused universal logic cell (100) may include transistors in basic cells (A to E) that are non-connected to a power supply (VDD) and/or a ground potential (VSS). Furthermore, unused universal logic cell (100) may include transistors in basic cells (A to E) that may provide a capacitor between a power supply (VDD) and a ground potential (VSS). In this way, off-leak current may be reduced and noise on a power line and/or a ground line may be reduced.
    • 已经公开了可以在不用作逻辑电路的通用逻辑单元(100)中具有减小的漏电流的通用逻辑模块。 通用逻辑模块可以包括可以形成有第二布线的通用逻辑单元(100),用于将通用逻辑单元(100)与形成有第一布线的基座配置相连接。 未使用的通用逻辑单元(100)可以包括未连接到电源(VDD)和/或接地电位(VSS)的基本单元(A至E)中的晶体管。 此外,未使用的通用逻辑单元(100)可以包括可在电源(VDD)和接地电位(VSS)之间提供电容器的基本单元(A至E)中的晶体管。 以这种方式,可以减少泄漏电流,并且可以减少电力线和/或接地线上的噪声。
    • 2. 发明授权
    • Clock signal distribution circuit
    • 时钟信号分配电路
    • US06696863B2
    • 2004-02-24
    • US10244507
    • 2002-09-17
    • Kenji YamamotoKazuhiro Nakajima
    • Kenji YamamotoKazuhiro Nakajima
    • H03K1900
    • G06F1/10
    • A tree wiring distributes an externally supplied clock signal to a plurality of first clock buffers. Routes of the tree wiring are designed so that the externally supplied clock signal can reach the plurality of first clock buffer substantially at the same time. The plurality of first clock buffers are connected to all intersections existing on a mesh wiring in one to one correspondence. The plurality of first clock buffers supply a clock signal supplied thereto through the tree wiring, to the mesh wiring. The mesh wiring protrudes from the intersections thereof which face toward outside by a predetermined length in order to keep load imposed on the plurality of first clock buffers uniform. A plurality of second clock buffers are connected to the mesh wiring, and supply clock signals supplied thereto from the plurality of first clock buffers through the mesh wiring, to a plurality of circuit elements.
    • 树形布线将外部提供的时钟信号分配给多个第一时钟缓冲器。 树线路的路径被设计成使得外部提供的时钟信号可以基本上同时到达多个第一时钟缓冲器。 多个第一时钟缓冲器以一一对应的方式连接到存在于网状布线上的所有交点。 多个第一时钟缓冲器通过树形布线将提供给其的时钟信号提供给网状布线。 网状布线从面向外侧的交点突出预定长度,以便保持施加在多个第一时钟缓冲器上的负载均匀。 多个第二时钟缓冲器连接到网状布线,并且通过网格布线将从多个第一时钟缓冲器提供的时钟信号提供给多个电路元件。
    • 8. 发明授权
    • Transparent electroconductive film and process for producing the same
    • 透明导电膜及其制造方法
    • US09297061B2
    • 2016-03-29
    • US12449303
    • 2008-02-15
    • Takashi KuchiyamaKenji Yamamoto
    • Takashi KuchiyamaKenji Yamamoto
    • B32B9/00C23C14/08C03C17/34
    • C23C14/086C03C17/3441C03C2217/944C03C2218/365
    • In a transparent electroconductive film including a transparent substrate and a transparent electroconductive oxide layer disposed on the transparent substrate, when the transparent electroconductive oxide layer is composed of zinc oxide, the surface resistivity of the transparent electroconductive oxide layer increases with time and thus it has been difficult to obtain a transparent electroconductive film stable against an environmental variation. Consequently, hard carbon films are provided on the surfaces of a transparent electroconductive oxide layer including at least one layer and containing zinc oxide as a main component in “the order of transparent substrate-hard carbon film-transparent electroconductive oxide layer-hard carbon film” or “the order of hard carbon film-transparent substrate-transparent electroconductive oxide layer-hard carbon film”. Alternatively, an organosilicon compound covering layer is provided on a surface of the transparent electroconductive oxide layer. Thereby, the water contact angle can be 75 degrees or more, and an increase in the resistivity of the transparent electroconductive oxide layer can be suppressed.
    • 在透明导电膜包括透明基板和透明导电氧化物层的透明导电膜上,当透明导电氧化物层由氧化锌组成时,透明导电氧化物层的表面电阻率随着时间的推移而增加, 难以获得对环境变化稳定的透明导电膜。 因此,在“透明基板 - 硬质碳膜透明导电氧化物层 - 硬质碳膜”的顺序,在包含至少一层并含有氧化锌作为主要成分的透明导电氧化物层的表面上设置硬质碳膜, 或“硬碳膜透明基板透明导电氧化物层 - 硬质碳膜的顺序”。 或者,在透明导电氧化物层的表面上设置有机硅化合物覆盖层。 因此,水接触角可以为75度以上,并且可以抑制透明导电氧化物层的电阻率的增加。