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1. 发明授权

US6118298A Structure for optionally cascading shift registers 有权
标题翻译：可选择级联移位寄存器的结构
公开(公告)号：US6118298A
公开(公告)日：2000-09-12
申请号：US253313
申请日：1999-02-18
申请人： Trevor J. Bauer , Bruce A. Newgard , William E. Allaire , Steven P. Young
发明人： Trevor J. Bauer , Bruce A. Newgard , William E. Allaire , Steven P. Young
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： G11C19/00 , H03K19/1736 , H03K19/17728 , H03K19/17736 , H03K19/17768
摘要： A set of logic elements can be configured as a cascadable shift register. In one embodiment, a logic element for an FPGA can be configured as any one of a random access memory, a cascadable shift register and a lookup table. The data-in path to the shift register includes a cascade multiplexer for optionally forming large shift registers using multiple logic elements. Each logic element includes a plurality of memory cells which are interconnected such that the data output of each memory cell can serve as the input to the next memory cell, causing the logic element to function as a shift register. The cascade multiplexer allows the last bit of one logic element to be connected to the first bit of the next logic element, bypassing any decode logic of the lookup table. Variable tap shift registers of arbitrary length can be created by cascading lookup tables of plural logic elements in series. The lookup table decode logic plus additional multiplexers can be used to select any memory cell (not necessarily the last memory cell) of the shift register.
摘要翻译：一组逻辑元件可以配置为可级联移位寄存器。在一个实施例中，用于FPGA的逻辑元件可以被配置为随机存取存储器，级联移位寄存器和查找表中的任何一个。到移位寄存器的数据输入路径包括级联多路复用器，用于可选地使用多个逻辑元件形成大移位寄存器。每个逻辑元件包括互连的多个存储器单元，使得每个存储器单元的数据输出可以用作到下一个存储单元的输入，使逻辑元件用作移位寄存器。级联多路复用器允许一个逻辑元件的最后一位连接到下一个逻辑元件的第一位，绕过查找表的任何解码逻辑。可以通过串联多个逻辑元件的查询表来创建任意长度的可变抽头移位寄存器。查找表解码逻辑加上附加多路复用器可用于选择移位寄存器的任何存储单元（不一定是最后一个存储单元）。

2. 发明授权

US06262597B1 FIFO in FPGA having logic elements that include cascadable shift registers 有权
标题翻译： FPGA中的FIFO具有包括可级联移位寄存器的逻辑元件
公开(公告)号：US06262597B1
公开(公告)日：2001-07-17
申请号：US09624515
申请日：2000-07-24
申请人： Trevor J. Bauer , Bruce A. Newgard , William E. Allaire , Steven P. Young
发明人： Trevor J. Bauer , Bruce A. Newgard , William E. Allaire , Steven P. Young
IPC分类号： H03K19177
CPC分类号： G11C19/00 , H03K19/1736 , H03K19/17728 , H03K19/17736 , H03K19/17768
摘要： A set of logic elements can be configured as a cascadable shift register. In one embodiment, a logic element for an FPGA can be configured as any one of a random access memory, a cascadable shift register and a lookup table. The data-in path to the shift register includes a cascade multiplexer for optionally forming large shift registers using multiple logic elements. Each logic element includes a plurality of memory cells which are interconnected such that the data output of each memory cell can serve as the input to the next memory cell, causing the logic element to function as a shift register. The cascade multiplexer allows the last bit of one logic element to be connected to the first bit of the next logic element, bypassing any decode logic of the lookup table. Variable tap shift registers of arbitrary length can be created by cascading lookup tables of plural logic elements in series. The lookup table decode logic plus additional multiplexers can be used to select any memory cell (not necessarily the last memory cell) of the shift register.
摘要翻译：一组逻辑元件可以配置为可级联移位寄存器。在一个实施例中，用于FPGA的逻辑元件可以被配置为随机存取存储器，级联移位寄存器和查找表中的任何一个。到移位寄存器的数据输入路径包括级联多路复用器，用于可选地使用多个逻辑元件形成大移位寄存器。每个逻辑元件包括互连的多个存储器单元，使得每个存储器单元的数据输出可以用作到下一个存储器单元的输入，使逻辑元件用作移位寄存器。级联多路复用器允许一个逻辑元件的最后一位连接到下一个逻辑元件的第一位，绕过查找表的任何解码逻辑。可以通过串联多个逻辑元件的查询表来创建任意长度的可变抽头移位寄存器。查找表解码逻辑加上附加多路复用器可用于选择移位寄存器的任何存储单元（不一定是最后一个存储单元）。

3. 发明授权

US08058905B1 Clock distribution to facilitate gated clocks 有权
标题翻译：时钟分配方便门控时钟
公开(公告)号：US08058905B1
公开(公告)日：2011-11-15
申请号：US12363722
申请日：2009-01-31
申请人： Matthew H. Klein , Richard W. Swanson , Trevor J. Bauer , Steven P. Young , Andy DeBaets
发明人： Matthew H. Klein , Richard W. Swanson , Trevor J. Bauer , Steven P. Young , Andy DeBaets
IPC分类号： H03K19/00 , H03K3/356
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various places in a hierarchical clock distribution network. The gated clock circuitry provides a clock signal gated by an enable signal to clocked elements. Configurable logic blocks (CLBs) comprising the clocked elements and programmable interconnect tiles are disposed in the gate array. Clock signals are distributed to the CLBs via a clock distribution network. Clock enable signals are provided corresponding to some of the clock signals. Clock buffers or drivers are provided within the clock distribution network that drive gated clock signals to CLBs. By disabling certain clocked elements using one or more embodiments of the invention when portions of the FPGA are inactive, dynamic power consumption is reduced.
摘要翻译：描述了便于在诸如现场可编程门阵列（FPGA）的可编程集成电路中分配门控时钟的电路和方法。通过在分层时钟分配网络中的不同位置提供门控时钟驱动器电路，可以在FPGA中实现动态功耗。门控时钟电路通过使能信号为时钟元件提供门控时钟信号。包括时钟元件和可编程互连瓦片的可配置逻辑块（CLB）设置在门阵列中。时钟信号通过时钟分配网络分发给CLB。对应于一些时钟信号提供时钟使能信号。在时钟分配网络中提供时钟缓冲器或驱动器，将门控时钟信号驱动到CLB。通过在FPGA的部分不活动时使用本发明的一个或多个实施例来禁用某些时钟元件，动态功耗降低。

4. 发明授权

US07617472B1 Regional signal-distribution network for an integrated circuit 有权
标题翻译：集成电路的区域信号分配网络
公开(公告)号：US07617472B1
公开(公告)日：2009-11-10
申请号：US12025637
申请日：2008-02-04
申请人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
发明人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054 , G06F2217/62
摘要： Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.
摘要翻译：描述区域信号的信号分布。集成电路包括全球信号分配网络，区域信号分配网络和区域缓冲器。区域缓冲区具有耦合在区域信号分配网络末端的输出。区域信号分配网络通过互连瓦片耦合到可配置的逻辑块。区域缓冲器耦合到具有区域时钟的输入/输出块。另外描述了用于区域信号分配的源同步接口。

5. 发明授权

US07402443B1 Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes 有权
标题翻译：使用产品选择代码为集成电路系列提供类似模具的方法部分禁用
公开(公告)号：US07402443B1
公开(公告)日：2008-07-22
申请号：US11333819
申请日：2006-01-17
申请人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
发明人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
IPC分类号： G01R31/26
CPC分类号： H01L27/11807 , H01L27/0207
摘要： A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.
摘要翻译：提供集成电路（IC）系列的方法包括：将第一产品选择代码（PSC）应用于第一IC芯片，将第二PSC应用于第二IC芯片，以及提供第三封装IC芯片。第一IC芯片包括第一和第二部分，它们都基于第一PSC而可操作。第二IC芯片是第一裸片的副本，但是第二部分由第二PSC不可操作。第三IC管芯基本上类似于第一管芯的第一部分。第二和第三包可以是相同的，并且包装的模具可以在系统中互换。当管芯是可编程逻辑器件（PLD）管芯时，第二和第三管芯使用与第一IC管芯的配置位流相同的配置位流。

6. 发明授权

US07312631B1 Structures and methods for avoiding hold time violations in a programmable logic device 有权
标题翻译：用于避免可编程逻辑器件中的保持时间违规的结构和方法
公开(公告)号：US07312631B1
公开(公告)日：2007-12-25
申请号：US11264405
申请日：2005-11-01
申请人： Trevor J. Bauer , Ramakrishna K. Tanikella , Steven P. Young
发明人： Trevor J. Bauer , Ramakrishna K. Tanikella , Steven P. Young
IPC分类号： H03K19/177 , H03K19/173 , H03K19/00
CPC分类号： H03K19/17736 , H03K19/00323
摘要： Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the source and destination of the signal. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.
摘要翻译：在PLD中实现的设计中避免持续时间违规的结构和方法。在可编程设备中，信号路径的延迟例如取决于信号的源和目的地之间的间隔而变化。在可编程互连结构和具有相对于源的时钟偏移的目的地逻辑元件之间提供可选的延迟元件。可选延迟元件由实现软件编程，以在必要时在信号路径上引入延迟以满足目的地逻辑元件的保持时间要求。可选延迟被设计为足够大，以克服即使对于最大可能的时钟偏移和尽可能小的信号延迟的保持时间违规。当没有发生保持时间违规时，可选的延迟元件被配置为绕过附加延迟，以避免对信号施加大的设置要求。

7. 发明授权

US07218139B1 Programmable integrated circuit providing efficient implementations of arithmetic functions 有权
标题翻译：提供算术功能的高效实现的可编程集成电路
公开(公告)号：US07218139B1
公开(公告)日：2007-05-15
申请号：US11151915
申请日：2005-06-14
申请人： Steven P. Young , Trevor J. Bauer
发明人： Steven P. Young , Trevor J. Bauer
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/1736 , G06F1/03 , G06F7/57
摘要： Efficient implementations of arithmetic functions in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate both an exclusive OR (XOR) function of first and second input signals and a second function. In some embodiments, the second function is simply the second input signal to the XOR function. In other embodiments, the second function is a different function optionally independent of the first and second input signals. The XOR function output drives the select terminal of a carry multiplexer, which selects between a carry in signal and one of the second input signal and the second function output signal to provide the carry out output signal. The sum or multiplier output value is provided by an XOR gate driven by the XOR function output and by the carry in signal, and can be optionally registered.
摘要翻译：可编程IC中算术功能的高效实现包括由双输出可编程功能发生器驱动的进位链多路复用器。具有两个输出信号的函数发生器被编程以产生第一和第二输入信号的异或（XOR）功能和第二功能。在一些实施例中，第二功能仅仅是到异或功能的第二输入信号。在其他实施例中，第二功能是可选地独立于第一和第二输入信号的不同功能。 XOR功能输出驱动进位多路复用器的选择端，它在进位信号和第二输入信号之一和第二功能输出信号之间进行选择，以提供进位输出信号。总和或乘法器输出值由XOR功能输出和进位输入信号驱动的异或门提供，可以任意注册。

8. 发明授权

US06933747B1 Structures and methods of testing interconnect structures in programmable logic devices 有权
标题翻译：在可编程逻辑器件中测试互连结构的结构和方法
公开(公告)号：US06933747B1
公开(公告)日：2005-08-23
申请号：US10684183
申请日：2003-10-10
申请人： Trevor J. Bauer , Steven P. Young , Ramakrishna K. Tanikella
发明人： Trevor J. Bauer , Steven P. Young , Ramakrishna K. Tanikella
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17764 , G01R31/2853 , G01R31/31723 , G01R31/318516 , H03K19/17736
摘要： Structures enabling the efficient testing of interconnect in programmable logic devices (PLDS), and methods utilizing these structures. A PLD includes a non-homogeneous array of programmable logic blocks and an array of standardized interconnect blocks, where the same interconnect block is used for different types of logic blocks. Coupled between each of the interconnect blocks and the associated logic block is a standardized test structure, allowing the same test configuration to be used for each interconnect block even though the interconnect blocks are associated with logic blocks of different types. In some embodiments, one or more types of logic blocks are not associated with standardized test structures. These logic blocks are coupled directly to their associated interconnect blocks, and are preferably of a type that can be configured to emulate the standardized test structure. Thus, by a correct application of configuration data all of the interconnect blocks display the same behavior.
摘要翻译：能够对可编程逻辑器件（PLDS）中的互连进行有效测试的结构以及利用这些结构的方法。 PLD包括可编程逻辑块的非均匀阵列和标准化互连块阵列，其中相同的互连块用于不同类型的逻辑块。在每个互连块和相关联的逻辑块之间耦合是标准化的测试结构，允许将相同的测试配置用于每个互连块，即使互连块与不同类型的逻辑块相关联。在一些实施例中，一个或多个类型的逻辑块不与标准化测试结构相关联。这些逻辑块直接耦合到它们相关联的互连块，并且优选地是可被配置为模拟标准化测试结构的类型。因此，通过配置数据的正确应用，所有互连块都显示相同的行为。

9. 发明授权

US06798241B1 Methods for aligning data and clock signals 有权
标题翻译：数据和时钟信号对齐的方法
公开(公告)号：US06798241B1
公开(公告)日：2004-09-28
申请号：US10376522
申请日：2003-02-27
申请人： Trevor J. Bauer , Steven P. Young , Christopher D. Ebeling , Jason R. Bergendahl , Arthur J. Behiel
发明人： Trevor J. Bauer , Steven P. Young , Christopher D. Ebeling , Jason R. Bergendahl , Arthur J. Behiel
IPC分类号： H03K19173
CPC分类号： H03K5/135 , H04L7/0337
摘要： Described are methods and circuits for aligning data and clock signals. Methods in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.
摘要翻译：描述了用于对准数据和时钟信号的方法和电路。根据一些实施例的方法将输入数据分成三个不同时间的数据信号：早期信号，中间信号和后期信号。三个数据信号的定时可以相对于时钟信号共同移动。此外，可以调整三个信号之间的时间间隔，使得早期和晚期信号限定包围中间信号的窗口。三个信号相对于时钟边沿对齐，以使中间数据信号在时钟边沿居中。可以监视早期和晚期信号以识别时钟和数据信号的相对定时的变化。一些实施例自动改变数据和/或时钟信号的定时，以使中间数据信号以时钟边缘为中心。

10. 发明授权

US06297665B1 FPGA architecture with dual-port deep look-up table RAMS 有权
标题翻译：具有双端口深度查询表RAMS的FPGA架构
公开(公告)号：US06297665B1
公开(公告)日：2001-10-02
申请号：US09574445
申请日：2000-05-19
申请人： Trevor J. Bauer , Steven P. Young
发明人： Trevor J. Bauer , Steven P. Young
IPC分类号： H03K19177
CPC分类号： H03K19/1736 , G11C19/00 , H03K19/17736 , H03K19/1776
摘要： A configurable logic block (CLB) having a plurality of identical configurable logic element (CLE) slices is provided. Each CLE slice includes a plurality of function generators (lookup tables) that can be configured to form a random access memory (RAM). The width and depth of the RAM are selectable by controlling the routing of signals within the CLE slices. A hierarchy of wide function multiplexers (F5, F6, and F7 multiplexers) are provided to selectively route read data values from the lookup tables. Another set of multiplexers is used to selectively route write data values to the lookup tables. These multiplexers can be configured to provide a single write data value to all of the lookup tables to form a deep RAM. Alternatively, these multiplexers can be configured to provide one write data value to half of the lookup tables, and another write data value to the other half of the lookup tables. This pattern repeats down to the level where these multiplexers can be configured to provide a different write data value to each of the lookup tables. A write control circuit is also provided in each CLE slice to provide write enable signals to the lookup tables in a manner consistent with the selected RAM size. Read and write addresses are provided in a manner that enables the CLB to be operated as a dual-port RAM having selectable width and depth.
摘要翻译：提供具有多个相同可配置逻辑元件（CLE）片的可配置逻辑块（CLB）。每个CLE切片包括可被配置成形成随机存取存储器（RAM）的多个功能发生器（查找表）。通过控制CLE切片内信号的路由可以选择RAM的宽度和深度。提供了多功能多路复用器（F5，F6和F7多路复用器）的层次结构，用于选择性地从查找表路由读取数据值。另一组多路复用器用于选择性地将写入数据值路由到查找表。这些多路复用器可以被配置为向所有查找表提供单个写数据值以形成深RAM。或者，这些多路复用器可以被配置为向查找表的一半提供一个写入数据值，并将另一个写入数据值提供给查找表的另一半。该模式重复到这些复用器可被配置为向每个查找表提供不同的写入数据值的级别。在每个CLE片中还提供写入控制电路，以与所选择的RAM大小一致的方式向查找表提供写使能信号。提供读写地址，使得CLB能够作为具有可选宽度和深度的双端口RAM来操作。

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