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1. 发明授权

US07042523B2 Video correction system and method using logarithmic conversion 有权
标题翻译：视频校正系统和方法采用对数转换
公开(公告)号：US07042523B2
公开(公告)日：2006-05-09
申请号：US10610150
申请日：2003-06-30
申请人： Towfique Haider , Walter H. Demmer , Bart DeCanne
发明人： Towfique Haider , Walter H. Demmer , Bart DeCanne
IPC分类号： H04N9/89
CPC分类号： H04N9/64 , H04N5/14 , H04N9/69
摘要： A video correction system and method are disclosed that provide video correction for an input signal. The system includes a logarithmic converter that creates a logarithmic representation of the input signal. A configurable corrector/converter comprises a plurality of associated components operative to process the logarithmic representation of the input signal. The configurable corrector/converter produces an output signal having at least one desirable signal characteristic. A switch control selects a configuration for the corrector/converter. The configuration indicates at least one of the plurality of associated components that will process the logarithmic representation.
摘要翻译：公开了提供输入信号的视频校正的视频校正系统和方法。该系统包括产生输入信号的对数表示的对数转换器。可配置的校正器/转换器包括多个相关联的组件，用于处理输入信号的对数表示。可配置校正器/转换器产生具有至少一个期望信号特性的输出信号。开关控制器选择校正器/转换器的配置。该配置指示将处理对数表示的多个关联组件中的至少一个。

2. 发明授权

US07425994B2 Video decoder with different signal types processed by common analog-to-digital converter 有权
标题翻译：具有由通用模数转换器处理的不同信号类型的视频解码器
公开(公告)号：US07425994B2
公开(公告)日：2008-09-16
申请号：US11047310
申请日：2005-01-31
申请人： Towfique Haider , Jason Meiners
发明人： Towfique Haider , Jason Meiners
IPC分类号： H03M1/12
CPC分类号： H03M1/1225
摘要： A video decoder (14). The decoder comprises an interface (30) for receiving a set of an integer number S of analog input signals at a same time. The decoder also comprises circuitry for processing the S analog input signals, and that circuitry comprises an integer number N of analog-to-digital converters (38x) for producing a set of the integer number S of digital signals. Each digital signal in the set of S of digital signals corresponds to a respective different one of the S analog input signal, and N is less than S. The decoder also comprises output circuitry (40x, 42x), coupled to the circuitry for processing, for providing each digital signal in the set of S of digital signals to a different respective output conductor.
摘要翻译：视频解码器（14）。解码器包括用于同时接收模拟输入信号的整数S的一个接口（30）。解码器还包括用于处理S模拟输入信号的电路，并且该电路包括整数N个模拟 - 数字转换器（38×X），用于产生数字的整数S的集合信号。数字信号组S中的每个数字信号对应于S模拟输入信号中的相应不同的一个，并且N小于S.解码器还包括输出电路（40 < 耦合到用于处理的电路，用于将S组数字信号中的每个数字信号提供给不同的相应输出导体。

3. 发明授权

US07787560B2 Smart antenna interface using only digital I/O supporting both mode A and mode B antenna operation as per CEA 909 standard using a single digital counter 有权
标题翻译：仅使用数字I / O的智能天线接口，使用单个数字计数器，根据CEA 909标准支持模式A和模式B天线操作
公开(公告)号：US07787560B2
公开(公告)日：2010-08-31
申请号：US11931518
申请日：2007-10-31
申请人： Towfique Haider , Kazunobu Shin
发明人： Towfique Haider , Kazunobu Shin
IPC分类号： H04L27/00
CPC分类号： H04N5/4401 , H04N21/436
摘要： This invention samples and transmits the CEA-909 standard smart antenna analog pulse train waveforms using only a digital I/O pin for both mode A and mode B operation. This invention implements the smart antenna interface based on a single digital programmable counter. This counter is programmable so that it can tolerate or produce wide variation of symbol width.
摘要翻译：本发明仅对模式A和模式B操作仅使用数字I / O引脚对CEA-909标准智能天线模拟脉冲串波形进行采样和传输。本发明实现了基于单个数字可编程计数器的智能天线接口。该计数器是可编程的，因此它可以容忍或产生符号宽度的宽泛变化。

4. 发明申请

US20060170825A1 Video decoder with different signal types processed by common analog-to-digital converter 有权
标题翻译：具有由通用模数转换器处理的不同信号类型的视频解码器
公开(公告)号：US20060170825A1
公开(公告)日：2006-08-03
申请号：US11047310
申请日：2005-01-31
申请人： Towfique Haider , Jason Meiners
发明人： Towfique Haider , Jason Meiners
IPC分类号： H03M1/12 , H04N5/268
CPC分类号： H03M1/1225
摘要： A video decoder (14). The decoder comprises an interface (30) for receiving a set of an integer number S of analog input signals at a same time. The decoder also comprises circuitry for processing the S analog input signals, and that circuitry comprises an integer number N of analog-to-digital converters (38x) for producing a set of the integer number S of digital signals. Each digital signal in the set of S of digital signals corresponds to a respective different one of the S analog input signal, and N is less than S. The decoder also comprises output circuitry (40x, 42x), coupled to the circuitry for processing, for providing each digital signal in the set of S of digital signals to a different respective output conductor.
摘要翻译：视频解码器（14）。解码器包括用于同时接收模拟输入信号的整数S的一个接口（30）。解码器还包括用于处理S模拟输入信号的电路，并且该电路包括整数N个模拟 - 数字转换器（38×X），用于产生数字的整数S的集合信号。数字信号组S中的每个数字信号对应于S模拟输入信号中的相应不同的一个，并且N小于S.解码器还包括输出电路（40 < 耦合到用于处理的电路，用于将S组数字信号中的每个数字信号提供给不同的相应输出导体。

5. 发明授权

US08249171B2 MPEG-2 transport stream packet synchronizer 有权
标题翻译： MPEG-2传输流分组同步器
公开(公告)号：US08249171B2
公开(公告)日：2012-08-21
申请号：US11558519
申请日：2006-11-10
申请人： Feng Ying , Towfique Haider
发明人： Feng Ying , Towfique Haider
IPC分类号： H04N7/12
CPC分类号： H04L7/0337 , H04L7/005 , H04N21/4305
摘要： A data synchronizer that receives an input stream of asynchronous digital data in packets, and provides an output stream of synchronous data in packets. The synchronizer includes a first memory unit and a second memory unit, each having a data input, a data output, a write clock input and a read clock input. A first switch is provided for switching connection of the input in alternating manner between the first memory unit input and the second memory unit input, and a second switch is provided for switching connection of the data synchronizer output in alternating manner between the first memory unit output and the second memory unit output. A write clock is provided to write clock inputs of the first and second memory units. The average data rate of the received valid data during the reception of the packet is determined, and a read clock is generated and provided to the first and second memory units at a rate corresponding to the average data rate of the received valid data bits during the reception of the packet being read. The switching of the first and second switches is controlled such that the switches switch between adjacent packets, with the second switch switching in opposite phase to that of the first switch.
摘要翻译：一种数据同步器，其以分组的形式接收异步数字数据的输入流，并提供分组中的同步数据的输出流。同步器包括第一存储器单元和第二存储器单元，每个具有数据输入，数据输出，写入时钟输入和读取时钟输入。第一开关被提供用于以第一存储器单元输入和第二存储器单元输入之间的交替方式切换输入的连接，并且提供第二开关，用于以交替的方式切换数据同步器输出的连接在第一存储器单元输出和第二存储器单元输出。提供写时钟来写入第一和第二存储器单元的时钟输入。确定在接收分组期间接收到的有效数据的平均数据速率，并且产生读时钟，并以对应于接收的有效数据比特的平均数据速率的速率将其提供给第一和第二存储器单元接收正在读取的数据包。控制第一和第二开关的切换，使得开关在相邻的分组之间切换，第二开关与第一开关相反地切换。

6. 发明申请

US20080112438A1 MPEG-2 TRANSPORT STREAM PACKET SYNCHRONIZER 有权
标题翻译： MPEG-2传输流分组同步器
公开(公告)号：US20080112438A1
公开(公告)日：2008-05-15
申请号：US11558519
申请日：2006-11-10
申请人： Feng Ying , Towfique Haider
发明人： Feng Ying , Towfique Haider
IPC分类号： H04J3/07
CPC分类号： H04L7/0337 , H04L7/005 , H04N21/4305
摘要： A data synchronizer that receives an input stream of asynchronous digital data in packets, and provides an output stream of synchronous data in packets. The synchronizer includes a first memory unit and a second memory unit, each having a data input, a data output, a write clock input and a read clock input. A first switch is provided for switching connection of the input in alternating manner between the first memory unit input and the second memory unit input, and a second switch is provided for switching connection of the data synchronizer output in alternating manner between the first memory unit output and the second memory unit output. A write clock is provided to write clock inputs of the first and second memory units. The average data rate of the received valid data during the reception of the packet is determined, and a read clock is generated and provided to the first and second memory units at a rate corresponding to the average data rate of the received valid data bits during the reception of the packet being read. The switching of the first and second switches is controlled such that the switches switch between adjacent packets, with the second switch switching in opposite phase to that of the first switch.
摘要翻译：一种数据同步器，其以分组的形式接收异步数字数据的输入流，并提供分组中的同步数据的输出流。同步器包括第一存储器单元和第二存储器单元，每个具有数据输入，数据输出，写入时钟输入和读取时钟输入。第一开关被提供用于以第一存储器单元输入和第二存储器单元输入之间的交替方式切换输入的连接，并且提供第二开关，用于以交替的方式切换数据同步器输出的连接在第一存储器单元输出和第二存储器单元输出。提供写时钟来写入第一和第二存储器单元的时钟输入。确定在接收分组期间接收到的有效数据的平均数据速率，并且产生读时钟，并以对应于接收的有效数据比特的平均数据速率的速率将其提供给第一和第二存储器单元接收正在读取的数据包。控制第一和第二开关的切换，使得开关在相邻的分组之间切换，第二开关与第一开关相反地切换。

7. 发明申请

US20080101517A1 Smart Antenna Interface Using Only Digital I/O Supporting Both Mode A and Mode B Antenna Operation as Per CEA 909 Standard Using a Single Digital Counter 有权
标题翻译：仅支持数字I / O的智能天线接口支持模式A和模式B天线操作按照CEA 909标准使用单个数字计数器
公开(公告)号：US20080101517A1
公开(公告)日：2008-05-01
申请号：US11931518
申请日：2007-10-31
申请人： Towfique Haider , Kazunobu Shin
发明人： Towfique Haider , Kazunobu Shin
IPC分类号： H04L7/02
CPC分类号： H04N5/4401 , H04N21/436
摘要： This invention samples and transmits the CEA-909 standard smart antenna analog pulse train waveforms using only a digital I/O pin for both mode A and mode B operation. This invention implements the smart antenna interface based on a single digital programmable counter. This counter is programmable so that it can tolerate or produce wide variation of symbol width.
摘要翻译：本发明仅对模式A和模式B操作仅使用数字I / O引脚对CEA-909标准智能天线模拟脉冲串波形进行采样和传输。本发明实现了基于单个数字可编程计数器的智能天线接口。该计数器是可编程的，因此它可以容忍或产生符号宽度的宽泛变化。

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