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1. 发明授权

US4694327A Digital phase locked loop stabilization circuitry using a secondary digital phase locked loop 失效
标题翻译：数字锁相环路稳定电路采用次级数字锁相环
公开(公告)号：US4694327A
公开(公告)日：1987-09-15
申请号：US845850
申请日：1986-03-28
申请人： Walter H. Demmer , Leopold A. Harwood , Chandrakant B. Patel , Alvin R. Balaban
发明人： Walter H. Demmer , Leopold A. Harwood , Chandrakant B. Patel , Alvin R. Balaban
IPC分类号： H03L7/06 , H03L7/087 , H03L7/099 , H03L7/22 , H04N9/45
CPC分类号： H04N9/45 , H03L7/0994 , H03L7/22
摘要： A digital television receiver includes a first phase locked loop which develops a sampling clock signal that is locked to the horizontal line synchronizing signal components of a composite video signal. A second digital phase locked loop is clocked by the sampling clock signal and develops a digital signal that is phase locked to the color burst signal. This digital signal is used as a regenerated color subcarrier signal to synchronously demodulate the chrominance components of the composite video signals into I and Q color difference signals. To compensate for frequency instability in the regenerated subcarrier signal caused by frequency instabilities in the line-locked clock signal, a third digital phase locked loop develops an output signal which is phase locked to a reference signal generated by a crystal controlled oscillator. Control signals from the third phase locked loop are applied to the second phase locked loop to substantially compensate for frequency instabilities in the regenerated subcarrier signal that are induced by the clock signals.
摘要翻译：数字电视接收机包括第一锁相环，其产生锁定到复合视频信号的水平线同步信号分量的采样时钟信号。第二数字锁相环由采样时钟信号计时，并产生与色同步信号锁相的数字信号。该数字信号用作再生彩色副载波信号，以将复合视频信号的色度分量同步解调为I和Q色差信号。为了补偿由线锁定时钟信号中的频率不稳定性引起的再生子载波信号中的频率不稳定性，第三数字锁相环产生锁相到由晶体振荡器产生的参考信号的输出信号。来自第三锁相环的控制信号被施加到第二锁相环，以基本上补偿由时钟信号引起的再生子载波信号中的频率不稳定性。

2. 发明授权

US07042523B2 Video correction system and method using logarithmic conversion 有权
标题翻译：视频校正系统和方法采用对数转换
公开(公告)号：US07042523B2
公开(公告)日：2006-05-09
申请号：US10610150
申请日：2003-06-30
申请人： Towfique Haider , Walter H. Demmer , Bart DeCanne
发明人： Towfique Haider , Walter H. Demmer , Bart DeCanne
IPC分类号： H04N9/89
CPC分类号： H04N9/64 , H04N5/14 , H04N9/69
摘要： A video correction system and method are disclosed that provide video correction for an input signal. The system includes a logarithmic converter that creates a logarithmic representation of the input signal. A configurable corrector/converter comprises a plurality of associated components operative to process the logarithmic representation of the input signal. The configurable corrector/converter produces an output signal having at least one desirable signal characteristic. A switch control selects a configuration for the corrector/converter. The configuration indicates at least one of the plurality of associated components that will process the logarithmic representation.
摘要翻译：公开了提供输入信号的视频校正的视频校正系统和方法。该系统包括产生输入信号的对数表示的对数转换器。可配置的校正器/转换器包括多个相关联的组件，用于处理输入信号的对数表示。可配置校正器/转换器产生具有至少一个期望信号特性的输出信号。开关控制器选择校正器/转换器的配置。该配置指示将处理对数表示的多个关联组件中的至少一个。

3. 发明授权

US4779128A Digital low-pass filter with improved frequency reduction characteristics 失效
标题翻译：具有改善频率降低特性的数字低通滤波器
公开(公告)号：US4779128A
公开(公告)日：1988-10-18
申请号：US927782
申请日：1986-11-05
申请人： Kurt-Joachim Johannes , Rolf-Dieter Gutsmann , Detlef Deutschmann , Otto Warmuth , Walter H. Demmer
发明人： Kurt-Joachim Johannes , Rolf-Dieter Gutsmann , Detlef Deutschmann , Otto Warmuth , Walter H. Demmer
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06 , H04N5/14 , H04N9/64
CPC分类号： H03H17/06 , H03H17/02 , H03H17/0219
摘要： The invention relates to a digital low-pass filter which effects a frequency reduction by a factor which is equal to the ratio w/2 between the frequency of the input signal and the frequency of the output signal, wherein w is an odd integer. The input signal is applied to m series-arranged registers. The input signal of the first and the output signals of all the registers are multiplied by coefficients. A change-over switch precedes an input of each multiplier, the change-over switch switching the coefficients symmetrically. The switching instants are always symmetrical relative to a reference sampling instant. The filter is particularly suitable for use in video signal processing, to reduce negative influences of an analog-to-digital converter.
摘要翻译：本发明涉及一种数字低通滤波器，其以等于输入信号的频率与输出信号的频率之比w / 2的因子来实现频率降低，其中w是奇整数。输入信号适用于m个串联排列的寄存器。所有寄存器的第一个和输出信号的输入信号乘以系数。切换开关先于每个乘法器的输入，转换开关对称地切换系数。切换时刻总是相对于参考采样时刻对称。滤波器特别适用于视频信号处理，以减少模数转换器的负面影响。

4. 发明授权

US4700217A Chrominance signal phase locked loop system for use in a digital television receiver having a line-locked clock signal 失效
标题翻译：色度信号锁相环系统，用于具有线锁时钟信号的数字电视接收机
公开(公告)号：US4700217A
公开(公告)日：1987-10-13
申请号：US893185
申请日：1986-08-05
申请人： Alvin R. Balaban , Walter H. Demmer , Leopold A. Harwood , Chandrakant B. Patel
发明人： Alvin R. Balaban , Walter H. Demmer , Leopold A. Harwood , Chandrakant B. Patel
IPC分类号： H04N9/45 , H04N9/66
CPC分类号： H04N9/45 , H04N9/66
摘要： A digital television receiver which uses a line-locked clock signal employs chrominance signal demodulation circuitry which produces a digital oscillatory signal that is locked in phase to the color reference burst signal component of the incoming video signals. An analog voltage controlled oscillator generates an oscillatory signal having a frequency of approximately twice the color subcarrier frequency. This signal is combined with the composite video signals and the combined signal is digitized by an analog to digital converter. The digitized oscillatory signal is separated from the combined digital signal and is used to synchronize a digital phase locked loop. The digital phase locked loop generates two quadrature phase related signals having frequencies that are one-half the frequency of the analog oscillatory signal. These two signals are used to synchronously demodulate the chrominance signal components of the incoming video signals to obtain two quadrature phase related color difference signals. The control signal for the voltage controlled oscillator is generated by subtracting the burst phase of the demodulated color difference signals from a reference phase and integrating the difference.
摘要翻译：使用线锁时钟信号的数字电视接收机采用色度信号解调电路，其生成与输入视频信号的颜色参考突发信号分量锁相的数字振荡信号。模拟压控振荡器产生具有大约是彩色副载波频率的两倍的频率的振荡信号。该信号与复合视频信号组合，组合信号由模数转换器数字化。数字振荡信号与组合数字信号分离，用于同步数字锁相环。数字锁相环产生频率为模拟振荡信号频率的一半的两个正交相位相关信号。这两个信号用于同步解调输入视频信号的色度信号分量，以获得两个正交相位相关的色差信号。压控振荡器的控制信号通过从参考相位减去解调色差信号的脉冲串相位而积分该差而产生。

5. 发明授权

US4641131A Circuit arrangement for converting a digital input signal into an analog output signal 失效
标题翻译：用于将数字输入信号转换成模拟输出信号的电路装置
公开(公告)号：US4641131A
公开(公告)日：1987-02-03
申请号：US878409
申请日：1986-06-20
申请人： Walter H. Demmer
发明人： Walter H. Demmer
IPC分类号： H03M1/76 , H03M1/00
CPC分类号： H03M1/066 , H03M1/808
摘要： In a circuit arrangement for converting a digital input signal into an analog output signal, comprising a voltage divider chain which, between its ends which are supplied by at least one reference voltage, has a plurality of taps which, under the control of the digital input signal, are connectable to an output for deriving the analog output signal, a reduction in the output resistance and also an increase of the bandwidth of the analog output signal are accomplished because of the fact that any possible value of the digital input signal (B0 . . . B7) connects at least two taps (A0 . . . A257) of the voltage divider chain (W1 . . . W257) together to the output.
摘要翻译：在用于将数字输入信号转换为模拟输出信号的电路装置中，包括一个分压器链，该分压器链在由至少一个参考电压提供的端部之间具有多个抽头，在数字输入的控制下信号可连接到用于导出模拟输出信号的输出，输出电阻的降低以及模拟输出信号的带宽的增加是可以实现的，因为数字输入信号（B0）的任何可能的值。 B7）将分压器链（W1 ... W257）的至少两个抽头（A0 ... A257）连接到输出端。

6. 发明授权

US4719504A Method for converting an analog picture signal into an amplitude-discrete output signal 失效
标题翻译：将模拟图像信号转换为振幅离散输出信号的方法
公开(公告)号：US4719504A
公开(公告)日：1988-01-12
申请号：US589432
申请日：1984-03-14
申请人： Peter E. Draheim , Walter H. Demmer , Otto L. Warmuth
发明人： Peter E. Draheim , Walter H. Demmer , Otto L. Warmuth
IPC分类号： H03M1/20 , H03M1/00 , H04N7/26 , H04N9/64 , H04N11/04 , H04N9/65 , H04N9/66
CPC分类号： H04N9/64 , H03M1/06 , H03M1/365
摘要： In a circuit arrangement for converting an analog picture signal, which corresponds to consecutive fields, into an amplitude-discrete output signal, which, in a comparison stage, compares the picture signal to a plurality of reference values and produces an amplitude-discrete intermediate signal at an output, a significant simplification of the circuit cost and design effort is accomplished with, at the same time, an improvement in the error cancellation by the fact that the change in the positions of the values of the picture signal and the reference values relative to each other corresponds to the sum of a fraction and a first integral number of value intervals.
摘要翻译：在用于将对应于连续场的模拟图像信号转换成幅度离散输出信号的电路装置中，其在比较级中将图像信号与多个参考值进行比较，并产生振幅离散中间信号在输出端，通过以下事实实现电路成本和设计工作的显着简化，同时通过图像信号的值和参考值的相对位置的改变来改进误差消除彼此对应于分数和第一整数值的值间隔的和。

7. 发明授权

US4703340A Frequency division multiplexed analog to digital converter 失效
标题翻译：频分复用模数转换器
公开(公告)号：US4703340A
公开(公告)日：1987-10-27
申请号：US858720
申请日：1986-05-02
申请人： Alvin R. Balaban , Leopold A. Harwood , Chandrakant B. Patel , Walter H. Demmer
发明人： Alvin R. Balaban , Leopold A. Harwood , Chandrakant B. Patel , Walter H. Demmer
IPC分类号： H04N5/14 , H04N9/64 , H04N11/04 , H04N5/00
CPC分类号： H04N9/64
摘要： A digital television receiver, having a line locked clock, includes a first digital phase locked loop which regenerates quadrature phase related subcarrier signals that are used to synchronously demodulate the chrominance signal components of composite video signals into color information signals. When nonstandard video signals (e.g., from a video tape recorder) are processed by the receiver, frequency instabilities in the line locked clock signal may cause the color information signals to be distorted. To compensate for this distortion, a second phase locked loop is synchronized to a reference signal generated by an analog oscillator. The analog reference signal is linearly added to baseband analog video signals provided by a tuner. The combined signals are digitized by an analog-to-digital converter and then filtered by parallel low-pass and band-pass filters to develop digital signals representing the video signals and the reference signal, respectively. The digital reference signal is used to synchronize the second phase locked loop, the control signals of which are used to compensate the first phase locked loop for frequency instabilities in the clock signal.
摘要翻译：具有线锁定时钟的数字电视接收机包括第一数字锁相环，其再生用于将复合视频信号的色度信号分量同步解调为彩色信息信号的正交相位相关副载波信号。当非标准视频信号（例如，来自录像机）由接收机处理时，线路锁定时钟信号中的频率不稳定性可能导致颜色信息信号失真。为了补偿这种失真，第二个锁相环与由模拟振荡器产生的参考信号同步。模拟参考信号线性地添加到由调谐器提供的基带模拟视频信号。组合的信号由模拟数字转换器数字化，然后通过并行低通和带通滤波器进行滤波，以分别开发表示视频信号和参考信号的数字信号。数字参考信号用于同步第二锁相环，其控制信号用于补偿第一锁相环中的时钟信号中的频率不稳定性。

8. 发明授权

US4642689A Increasing the resolution of a digitized, time-dependent signal 失效
标题翻译：增加数字化，时间依赖信号的分辨率
公开(公告)号：US4642689A
公开(公告)日：1987-02-10
申请号：US684201
申请日：1984-12-20
申请人： Walter H. Demmer
发明人： Walter H. Demmer
IPC分类号： H03M1/20 , G06T1/00 , H03H17/00 , H03H17/02 , H03M1/08 , H04N7/12 , H04N5/14
CPC分类号： G06T1/0007
摘要： In a method of increasing the resolution of a digitized time-dependent signal, particularly a picture signal, which consists of a sequence of sampling values, teaches the forming at one sampling value an associated mean value with higher resolution. The associated mean value is formed from the sampling value and at least one succeeding and/or preceding sampling value. When the sampling value is replaced by the associated mean value, obliteration of rapid signal changes is eliminated; and circuit complexity is minimized by the fact that a sampling value is replaced by the associated mean value only when these two values differ from one another by no more than a preset amount. A circuit for implementing this method is also disclosed.
摘要翻译：在增加数字化时间相关信号的分辨率的方法中，特别是由一系列采样值组成的图像信号，教导了以一个采样值形成具有较高分辨率的相关联的平均值。相关联的平均值由采样值和至少一个后续和/或之前的采样值形成。当采样值被相关联的平均值代替时，消除快速信号变化的消除; 并且只有当这两个值彼此不同于预设量时，采样值被相关联的平均值代替，则电路复杂度最小化。还公开了一种用于实现该方法的电路。

9. 发明授权

US4570126A FM Demodulator using interpolation to approximate zero crossings 失效
标题翻译： FM解调器使用插值逼近过零点
公开(公告)号：US4570126A
公开(公告)日：1986-02-11
申请号：US507202
申请日：1983-06-23
申请人： Walter H. Demmer , Rolf D. Gutsmann , Norbert A. Bergs , Ingolf B. Heinemann , Otto L. Warmuth
发明人： Walter H. Demmer , Rolf D. Gutsmann , Norbert A. Bergs , Ingolf B. Heinemann , Otto L. Warmuth
IPC分类号： H03D3/00
CPC分类号： H03D3/006 , H03D2200/0062 , H03D2200/0064
摘要： For determining the half-cycle durations of the input signal which is presented as a sequence of sampled values, its zero crossings are approximated by lines which interconnect the two sampled values of different signs on both sides of the zero crossing. The half-cycle duration is derived from the number of sampled values within a period, i.e. between two consecutive zero crossings, and from the time intervals at the beginning and end of each half-cycle determined by the intersection of the approximation line with the axis. The time intervals at the beginning and end of each period are corrected for a more accurate determination of the duration and the time intervals during which the values of the individual half-cycle durations are stored, are made to approximate to these half-cycle durations. The instantaneous frequency of the input signal is determined from the values of the half-cycle durations which have thus been shifted in time by forming the reciprocal.
摘要翻译：为了确定作为采样值序列呈现的输入信号的半周期持续时间，其过零点通过在过零点两侧互连不同符号的两个采样值的线近似。半周期持续时间是从一个周期内的抽样值的数量，即在两个连续过零点之间，从每个半周期开始和结束的时间间隔，由近似线与轴的交点确定的。校正每个周期的开始和结束的时间间隔，以更准确地确定持续时间和存储各个半周期持续时间的值的时间间隔，使其接近于这些半周期持续时间。输入信号的瞬时频率根据通过形成倒数在时间上偏移的半周期持续时间的值来确定。

10. 发明授权

US4686560A Phase locked loop system including analog and digital components 失效
标题翻译：锁相环系统包括模拟和数字组件
公开(公告)号：US4686560A
公开(公告)日：1987-08-11
申请号：US868567
申请日：1986-05-30
申请人： Alvin R. Balaban , Chandrakant B. Patel , Walter H. Demmer , Leopold A. Harwood
发明人： Alvin R. Balaban , Chandrakant B. Patel , Walter H. Demmer , Leopold A. Harwood
IPC分类号： H03L7/06 , H03L7/087 , H04L5/06 , H04N9/45 , H04N9/66
CPC分类号： H04N9/45 , H03L7/087
摘要： A digital television receiver, having a line-locked clock, includes a partly digital, partly analog phase locked loop. This phase locked loop regenerates two quadrature phase related subcarrier signals that are used to synchronously demodulate the chrominance signal components of the composite video signals into two color informaiton signals. The phase locked loop includes an analog voltage controlled oscillator which generates a signal that is independent of any frequency instability in the line locked clock signal. An analog-to-digital converter digitizes this signal to provide one of the subcarrier signals. This subcarrier signal is applied to a read-only memory to generate the second subcarrier signal. The two color information signals are obtained by multiplying the chrominance signals by the first and second subcarrier signals. A phase comparator determines the phase of the vector sum of the two color information signals and compares this against a desired phase value to generate a phase difference signal. The phase difference signal is filtered and applied to a digital-to-analog converter which provides the frequency control signal for the analog voltage controlled oscillator. In a second embodiment of the invention, a tracking filter is inserted at the output port of the analog-to-digital converter to allow the quantization resolution of the analog-to-digital to be reduced without affecting the performance of the phase locked loop.
摘要翻译：具有线锁时钟的数字电视接收机包括部分数字部分模拟锁相环。该锁相环再生两个相位相关的副载波信号，用于将复合视频信号的色度信号分量同步解调成两个彩色信号信号。锁相环包括模拟压控振荡器，其产生独立于线路锁定时钟信号中的任何频率不稳定性的信号。模数转换器对该信号进行数字化以提供副载波信号之一。该子载波信号被施加到只读存储器以产生第二副载波信号。通过将色度信号乘以第一和第二子载波信号来获得两个颜色信息信号。相位比较器确定两个颜色信息信号的矢量和的相位，并将其与期望的相位值进行比较以产生相位差信号。相位差信号被滤波并施加到数模转换器，该转换器为模拟压控振荡器提供频率控制信号。在本发明的第二实施例中，跟踪滤波器被插入在模数转换器的输出端口，以允许在不影响锁相环的性能的情况下降低模拟数字的量化分辨率。

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