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1. 发明授权

US07425994B2 Video decoder with different signal types processed by common analog-to-digital converter 有权
标题翻译：具有由通用模数转换器处理的不同信号类型的视频解码器
公开(公告)号：US07425994B2
公开(公告)日：2008-09-16
申请号：US11047310
申请日：2005-01-31
申请人： Towfique Haider , Jason Meiners
发明人： Towfique Haider , Jason Meiners
IPC分类号： H03M1/12
CPC分类号： H03M1/1225
摘要： A video decoder (14). The decoder comprises an interface (30) for receiving a set of an integer number S of analog input signals at a same time. The decoder also comprises circuitry for processing the S analog input signals, and that circuitry comprises an integer number N of analog-to-digital converters (38x) for producing a set of the integer number S of digital signals. Each digital signal in the set of S of digital signals corresponds to a respective different one of the S analog input signal, and N is less than S. The decoder also comprises output circuitry (40x, 42x), coupled to the circuitry for processing, for providing each digital signal in the set of S of digital signals to a different respective output conductor.
摘要翻译：视频解码器（14）。解码器包括用于同时接收模拟输入信号的整数S的一个接口（30）。解码器还包括用于处理S模拟输入信号的电路，并且该电路包括整数N个模拟 - 数字转换器（38×X），用于产生数字的整数S的集合信号。数字信号组S中的每个数字信号对应于S模拟输入信号中的相应不同的一个，并且N小于S.解码器还包括输出电路（40 < 耦合到用于处理的电路，用于将S组数字信号中的每个数字信号提供给不同的相应输出导体。

2. 发明申请

US20060218213A1 Optimization technique for FIR and IIR filter design 审中-公开
标题翻译： FIR和IIR滤波器设计的优化技术
公开(公告)号：US20060218213A1
公开(公告)日：2006-09-28
申请号：US11089178
申请日：2005-03-24
申请人： Shereef Shehata , Jason Meiners
发明人： Shereef Shehata , Jason Meiners
IPC分类号： G06F17/10
CPC分类号： H03H17/0227 , H03H17/04 , H03H17/06 , H03H2017/0072
摘要： A method for optimizing a digital filter that produces an output signal from samples of an input signal is configured with filter coefficients that are selected by a prescribed filter coefficient search. The filter coefficient search uses a pre-scaling constant or an additive constant with the filter coefficients and canonical signed digits to reduce filter cost or filter execution time. The coefficient search includes a precision for the filter coefficients and an allowable number of nonzero digits for each coefficient to produce a filter coefficient set with a reduced overall number of nonzero digits. The resulting filter can generally be implemented with substantially less integrated circuit die area than that obtainable with previous design approaches.
摘要翻译：用于优化从输入信号的样本产生输出信号的数字滤波器的方法被配置有通过规定的滤波器系数搜索选择的滤波器系数。滤波器系数搜索使用预定标常数或加法常数与滤波器系数和规范有符号数字来降低滤波器成本或滤波器执行时间。系数搜索包括滤波器系数的精度和每个系数的允许非零数字数，以产生具有减少的非零数字总数的滤波器系数。所得到的滤波器通常可以用比以前的设计方法可获得的小得多的集成电路管芯面积来实现。

3. 发明授权

US07511769B2 Interframe noise reduction for video 有权
标题翻译：视频帧间降噪
公开(公告)号：US07511769B2
公开(公告)日：2009-03-31
申请号：US11109290
申请日：2005-04-19
申请人： Karl Hertzian Renner , Shereef Shehata , Jason Meiners , Weider Peter Chang
发明人： Karl Hertzian Renner , Shereef Shehata , Jason Meiners , Weider Peter Chang
IPC分类号： H04N5/21 , H04N1/409 , H04N1/58
CPC分类号： H04N9/646 , H04N5/21 , H04N5/911
摘要： A system to reduce noise includes a noise measurement device that provides a measure of noise associated with a digital input video signal. A noise reduction filter provides a noise-reduced digital output video signal corresponding to the luma and chroma of the digital input video signal. The noise reduction filter has a parameter that varies on a pixel basis for the component of the digital input video signal as a function of the measure of noise. The range and sensitivity of the noise reduction can be user programmable.
摘要翻译：降低噪声的系统包括提供与数字输入视频信号相关联的噪声测量的噪声测量装置。噪声降低滤波器提供对应于数字输入视频信号的亮度和色度的噪声降低的数字输出视频信号。噪声降低滤波器具有作为噪声测量的函数的数字输入视频信号的分量基于像素变化的参数。降噪的范围和灵敏度可以由用户编程。

4. 发明授权

US07356107B2 Flying-adder frequency synthesizer-based digital-controlled oscillator and video decoder including the same 有权
标题翻译：基于飞加法器的频率合成器数字控制振荡器和视频解码器包括相同
公开(公告)号：US07356107B2
公开(公告)日：2008-04-08
申请号：US10829770
申请日：2004-04-22
申请人： Liming Xiu , Jason Meiners
发明人： Liming Xiu , Jason Meiners
IPC分类号： H04L7/00 , H04L7/04
CPC分类号： H03L7/00
摘要： A video decoder (52, 152) including a digital-control oscillator (DCO) (60, 160) is disclosed. The DCO (60, 160) includes a first flying-adder frequency synthesis circuit (74S) that measures an input signal frequency, such as the horizontal sync frequency of an input video signal. A frequency control word (FREQ) is generated in response to this input signal frequency, and is applied to a second flying-adder frequency synthesis circuit (74), which in turn selects the appropriate phases for leading and trailing edges of the output clock signal (PIX_CLK). Phase tuning of the output clock signal (PIX_CLK) can be effected by using an alternate flying-adder frequency synthesis circuit (74′) architecture, in combination with a phase signal (PH) generated by a digital controller (61). Multiple phase-tuned sample clocks (PIX_CLK_A, PIX_CLK_B, PIX_CLK_C) can be similarly generated from multiple flying-adder frequency synthesis circuits (174A, 174B, 174C), each controlled by the frequency control word (FREQ) and a corresponding phase signal (PHA, PHB, PHC). Video mode control logic (65, 165) can also be implemented by way of a similar DCO architecture. The DCO (60) may be used to generate a clock signal at a large frequency multiple relative to the input signal, outside of the video decoder context.
摘要翻译：公开了一种包括数字控制振荡器（DCO）（60,160）的视频解码器（52,152）。 DCO（60,160）包括测量输入信号频率（例如输入视频信号的水平同步频率）的第一飞行加法器频率合成电路（74S）。响应于该输入信号频率产生频率控制字（FREQ），并将其施加到第二飞行加法器频率合成电路（74），该第二飞行加法器频率合成电路又选择输出时钟信号的前沿和后沿的适当相位（PIX_CLK）。输出时钟信号（PIX_CLK）的相位调谐可以通过与由数字控制器（61）产生的相位信号（PH）结合使用替代的飞行加法器频率合成电路（74'）架构来实现。多个相位调制的采样时钟（PIX_CLK_A，PIX_CLK_B，PIX_CLK_C）可以类似地从多个飞越加法器频率合成电路（174A，174B，174C）产生，每个由频率控制字（FREQ）控制的相应相位信号（PHA，PHB，PHC）。视频模式控制逻辑（65,165）也可以通过类似的DCO架构来实现。 DCO（60）可用于在视频解码器上下文之外产生相对于输入信号大的频率倍数的时钟信号。

5. 发明申请

US20050122432A1 Method for generating a representation of a particular signal among a plurality of signals representing lines in a display 有权
标题翻译：用于在表示显示中的线的多个信号中产生特定信号的表示的方法
公开(公告)号：US20050122432A1
公开(公告)日：2005-06-09
申请号：US10726872
申请日：2003-12-03
申请人： Jason Meiners
发明人： Jason Meiners
IPC分类号： H04N9/77 , H04N9/78
CPC分类号： H04N9/78
摘要： A method for generating a representation of a particular signal among video signals representing a display, the signals including a first component having a first bandwidth and a second component having a smaller second bandwidth, includes the steps of: (a) measuring first samples of the first component outside the second bandwidth for an interval in each signal; (b)measuring second samples of the second component inside the second bandwidth for the interval; (c) establishing factors based upon first samples; (d) establishing filter modes based upon second samples; (e) establishing a correlation between factors and filter modes; (f) filtering the signals using a selected filter mode; (g) identifying a selected factor according to the correlation for the selected filter mode; (h) employing the selected factor for weighted mixing of the samples to generate the representation for the time interval; and (g) repeating steps (a) through (h) until the representation is completed.
摘要翻译：一种用于在表示显示器的视频信号中产生特定信号的表示的方法，所述信号包括具有第一带宽的第一分量和具有较小第二带宽的第二分量，包括以下步骤：（a）测量第在第二带宽之外的每个信号中的间隔的第一分量; （b）测量所述间隔的所述第二带宽内的所述第二分量的第二样本; （c）建立基于第一样本的因素; （d）基于第二样本建立滤波器模式; （e）建立因素与过滤模式之间的相关性; （f）使用选择的滤波器模式对信号进行滤波; （g）根据所选择的滤波器模式的相关性识别选择的因子; （h）采用所选因子对样本进行加权混合以产生时间间隔的表示; 和（g）重复步骤（a）至（h）直到表示完成。

6. 发明申请

US20050018080A1 Equilibrium based horizontal sync detector for video decoder 有权
标题翻译：用于视频解码器的基于平衡的水平同步检测器
公开(公告)号：US20050018080A1
公开(公告)日：2005-01-27
申请号：US10623232
申请日：2003-07-18
申请人： Karl Renner , Walter Demmer , Jason Meiners
发明人： Karl Renner , Walter Demmer , Jason Meiners
IPC分类号： H04N5/10 , H03L7/00
CPC分类号： H04N5/10
摘要： The present invention discloses a horizontal sync detector circuit (10) comprising a filter portion (12), an equilibrium accumulator portion (14) coupled to the filter portion (12), a horizontal sync detector portion (16) coupled to the filter portion (12) and to the equilibrium accumulator portion (14), and an output logic portion (18) coupled to the horizontal sync detector portion (16), the output logic portion (18) adapted to produce a phase error (116) based on a combination of a coarse phase error (108) and a fine phase error (112).
摘要翻译：本发明公开了一种包括滤波器部分（12），耦合到滤波器部分（12）的平衡累加器部分（14）的水平同步检测器电路（10），耦合到滤波器部分的水平同步检测器部分 12）和平衡累加器部分（14）以及耦合到水平同步检测器部分（16）的输出逻辑部分（18），输出逻辑部分（18）适于产生基于粗相位误差（108）和精细相位误差（112）的组合。

7. 发明授权

US09380260B2 Multichannel video port interface using no external memory 有权
标题翻译：多通道视频端口接口，不使用外部存储器
公开(公告)号：US09380260B2
公开(公告)日：2016-06-28
申请号：US12691441
申请日：2010-01-21
申请人： Jason Meiners , James Nave , Xiaodong Wu , Hyunkeun Kim , Todd Hiers
发明人： Jason Meiners , James Nave , Xiaodong Wu , Hyunkeun Kim , Todd Hiers
IPC分类号： H04N7/08 , H04N21/234 , H04N21/2365 , H04N21/434 , H04N21/44 , H04N7/015
CPC分类号： H04N7/0806 , H04N7/015 , H04N21/234 , H04N21/2365 , H04N21/4347 , H04N21/44
摘要： This invention is a video line encapsulation protocol which allows multiple low definition video streams to be combined into a single super frame of high definition video data. Each super frame is formed of individual lines from plural lower definition video input signals. The high definition video frames include meta data in each line identifying the video input source, line and frame. This meta data enables the super frames to be separated into their component input signals within a video processing digital signal processor.
摘要翻译：本发明是允许将多个低清晰度视频流组合成高清晰度视频数据的单个超帧的视频行封装协议。每个超级帧由多个低分辨率视频输入信号的各个线形成。高分辨率视频帧包括识别视频输入源，行和帧的每行中的元数据。该元数据使超帧能够在视频处理数字信号处理器内分离成其分量输入信号。

8. 发明申请

US20060232709A1 Interframe noise reduction for video 有权
公开(公告)号：US20060232709A1
公开(公告)日：2006-10-19
申请号：US11109290
申请日：2005-04-19
申请人： Karl Renner , Shereef Shehata , Jason Meiners , Weider Chang
发明人： Karl Renner , Shereef Shehata , Jason Meiners , Weider Chang
IPC分类号： H04N5/00 , H04N9/78
CPC分类号： H04N9/646 , H04N5/21 , H04N5/911
摘要： A system to reduce noise includes a noise measurement device that provides a measure of noise associated with a digital input video signal. A noise reduction filter provides a noise-reduced digital output video signal corresponding to the luma and chroma of the digital input video signal. The noise reduction filter has a parameter that varies on a pixel basis for the component of the digital input video signal as a function of the measure of noise. The range and sensitivity of the noise reduction can be user programmable.

9. 发明授权

US07023497B2 Clamping circuit with wide input dynamic range for video or other AC coupled signals 有权
标题翻译：用于视频或其他交流耦合信号的宽输入动态范围的钳位电路
公开(公告)号：US07023497B2
公开(公告)日：2006-04-04
申请号：US10210473
申请日：2002-07-31
申请人： Lieyi Fang , Haydar Bilhan , Gonggui Xu , Ramesh Chandrasekaran , Feng Ying , Erkan Bilhan , Jason Meiners
发明人： Lieyi Fang , Haydar Bilhan , Gonggui Xu , Ramesh Chandrasekaran , Feng Ying , Erkan Bilhan , Jason Meiners
IPC分类号： H04N5/16
CPC分类号： H04N5/185 , H04N5/18
摘要： A clamping circuit disclosed herein has two modes of operation which include both a bottom level and mid-level clamping mode for clamping automatically onto the sync tip of a video signal and customizably clamping onto the front porch, back porch/pedestal or anywhere within the signal. The clamping circuit (400) includes a clamping capacitor (404) that couples to an automatic clamping circuit portion (405) to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage (Vref1) of a first clamping pulse signal during an automatic clamping mode of operation. The automatic clamping portion (405) connects to the customizable clamping circuit portion (411) to clamp any portion of the video input signal to a second predetermined reference voltage (Vref2) of a second clamping pulse signal during a customizable clamping mode of operation. A buffer (416) connects between the customizable clamping circuit portion and the output node of the clamping circuit.
摘要翻译：本文公开的钳位电路具有两种操作模式，其包括底部电平和中间级钳位模式，用于自动钳位在视频信号的同步端上，并可自定义地夹紧在前沿，后沿/基座或信号内的任何地方。钳位电路（400）包括钳位电容器（404），其耦合到自动钳位电路部分（405）以自动将视频输入信号的同步脉冲钳位到第一预定参考电压（V SUB ref1 ）在自动钳位操作模式期间的第一钳位脉冲信号。自动夹紧部分（405）连接到可定制的钳位电路部分（411），以将视频输入信号的任何部分钳位到第二钳位脉冲信号的第二预定参考电压（V SUB ref2

10. 发明申请

US20050162552A1 Flying-adder frequency synthesizer-based digital-controlled oscillator and video decoder including the same 有权
标题翻译：基于飞加法器的频率合成器数字控制振荡器和视频解码器包括相同
公开(公告)号：US20050162552A1
公开(公告)日：2005-07-28
申请号：US10829770
申请日：2004-04-22
申请人： Liming Xiu , Jason Meiners
发明人： Liming Xiu , Jason Meiners
IPC分类号： H03L7/00 , H04N5/06
CPC分类号： H03L7/00
摘要： A video decoder (52, 152) including a digital-control oscillator (DCO) (60, 160) is disclosed. The DCO (60, 160) includes a first flying-adder frequency synthesis circuit (74S) that measures an input signal frequency, such as the horizontal sync frequency of an input video signal. A frequency control word (FREQ) is generated in response to this input signal frequency, and is applied to a second flying-adder frequency synthesis circuit (74), which in turn selects the appropriate phases for leading and trailing edges of the output clock signal (PIX_CLK). Phase tuning of the output clock signal (PIX_CLK) can be effected by using an alternate flying-adder frequency synthesis circuit (74′) architecture, in combination with a phase signal (PH) generated by a digital controller (61). Multiple phase-tuned sample clocks (PIX_CLK_A, PIX_CLK_B, PIX_CLK_C) can be similarly generated from multiple flying-adder frequency synthesis circuits (174A, 174B, 174C), each controlled by the frequency control word (FREQ) and a corresponding phase signal (PHA, PHB, PHC). Video mode control logic (65, 165) can also be implemented by way of a similar DCO architecture. The DCO (60) may be used to generate a clock signal at a large frequency multiple relative to the input signal, outside of the video decoder context.
摘要翻译：公开了一种包括数字控制振荡器（DCO）（60,160）的视频解码器（52,152）。 DCO（60,160）包括测量输入信号频率（例如输入视频信号的水平同步频率）的第一飞行加法器频率合成电路（74S）。响应于该输入信号频率产生频率控制字（FREQ），并将其施加到第二飞行加法器频率合成电路（74），该第二飞行加法器频率合成电路又选择输出时钟信号的前沿和后沿的适当相位（PIX_CLK）。输出时钟信号（PIX_CLK）的相位调谐可以通过与由数字控制器（61）产生的相位信号（PH）结合使用替代的飞行加法器频率合成电路（74'）架构来实现。多个相位调制的采样时钟（PIX_CLK_A，PIX_CLK_B，PIX_CLK_C）可以类似地从多个飞越加法器频率合成电路（174A，174B，174C）产生，每个由频率控制字（FREQ）控制的相应相位信号（PHA，PHB，PHC）。视频模式控制逻辑（65,165）也可以通过类似的DCO架构来实现。 DCO（60）可用于在视频解码器上下文之外产生相对于输入信号大的频率倍数的时钟信号。

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