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1. 发明申请

US20080179659A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080179659A1
公开(公告)日：2008-07-31
申请号：US12021003
申请日：2008-01-28
申请人： Toshiyuki Enda , Hiroyoshi Tanimoto , Takashi Izumida
发明人： Toshiyuki Enda , Hiroyoshi Tanimoto , Takashi Izumida
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, said first select gate transistor having a first pillar semiconductor, a first gate insulation layer formed around said first pillar semiconductor and a first gate electrode being formed around said first gate insulation layer; said memory cell having a second pillar semiconductor, a first insulation layer formed around said second pillar semiconductor, a storage layer formed around said first insulation layer, a second insulation layer formed around said storage layer and first to nth electrodes (n is a natural number 2 or more) being formed around said second insulation layer, said first to nth electrodes being spread in two dimensions respectively, said second select gate transistor having a third pillar semiconductor, a second gate insulation layer formed around said third pillar semiconductor and a second gate electrode being formed around said second gate insulation layer, and a channel region of at least either said first select gate transistor or said second select gate transistor formed by an opposite conductive type semiconductor to a source region and a drain region.
摘要翻译：关于本发明的一个实施例的非易失性半导体存储器件包括衬底，形成在所述衬底上的多个存储器串，所述存储器串具有第一选择栅晶体管，多个存储单元和第二选择栅晶体管，所述第一选择具有第一柱状半导体的栅极晶体管，形成在所述第一柱状半导体周围的第一栅极绝缘层和围绕所述第一栅极绝缘层形成的第一栅极电极; 所述存储单元具有第二柱状半导体，围绕所述第二柱状半导体形成的第一绝缘层，围绕所述第一绝缘层形成的存储层，形成在所述存储层和第一至第n电极周围的第二绝缘层（n为自然数） 2个或更多个），所述第一至第n电极分别以两维扩展，所述第二选择栅晶体管具有第三柱半导体，围绕所述第三柱半导体形成的第二栅绝缘层和第二栅极形成在所述第二栅极绝缘层周围的电极，以及至少所述第一选择栅极晶体管或所述第二选择栅极晶体管的沟道区域，所述沟道区域由相对的导电型半导体形成为源极区域和漏极区域。

2. 发明授权

US08610282B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08610282B2
公开(公告)日：2013-12-17
申请号：US13109086
申请日：2011-05-17
申请人： Takashi Kurusu , Takashi Izumida , Hiroyoshi Tanimoto , Nobutoshi Aoki
发明人： Takashi Kurusu , Takashi Izumida , Hiroyoshi Tanimoto , Nobutoshi Aoki
IPC分类号： H01L23/13
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76838 , H01L23/528 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.
摘要翻译：在一个实施例中，半导体器件包括衬底和设置在衬底上方的相同互连层中的多个互连。该装置还包括多个绝缘体，其设置成埋在多个互连件之间。此外，多个互连包括互连组，其中连续排列2N个或更多个互连，使得各互连的两个侧表面之间的线边缘粗糙度（LER）的相关系数为正，其中N为4或更大的整数。

3. 发明授权

US07956408B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07956408B2
公开(公告)日：2011-06-07
申请号：US12021003
申请日：2008-01-28
申请人： Toshiyuki Enda , Hirosyoshi Tanimoto , Takashi Izumida
发明人： Toshiyuki Enda , Hirosyoshi Tanimoto , Takashi Izumida
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, said first select gate transistor having a first pillar semiconductor, a first gate insulation layer formed around said first pillar semiconductor and a first gate electrode being formed around said first gate insulation layer; said memory cell having a second pillar semiconductor, a first insulation layer formed around said second pillar semiconductor, a storage layer formed around said first insulation layer, a second insulation layer formed around said storage layer and first to nth electrodes (n is a natural number 2 or more) being formed around said second insulation layer, said first to nth electrodes being spread in two dimensions respectively, said second select gate transistor having a third pillar semiconductor, a second gate insulation layer formed around said third pillar semiconductor and a second gate electrode being formed around said second gate insulation layer, and a channel region of at least either said first select gate transistor or said second select gate transistor formed by an opposite conductive type semiconductor to a source region and a drain region.
摘要翻译：关于本发明的一个实施例的非易失性半导体存储器件包括衬底，形成在所述衬底上的多个存储器串，所述存储器串具有第一选择栅晶体管，多个存储单元和第二选择栅晶体管，所述第一选择具有第一柱状半导体的栅极晶体管，形成在所述第一柱状半导体周围的第一栅极绝缘层和围绕所述第一栅极绝缘层形成的第一栅极电极; 所述存储单元具有第二柱状半导体，围绕所述第二柱状半导体形成的第一绝缘层，围绕所述第一绝缘层形成的存储层，形成在所述存储层和第一至第n电极周围的第二绝缘层（n为自然数） 2个或更多个），所述第一至第n电极分别以两维扩展，所述第二选择栅晶体管具有第三柱半导体，围绕所述第三柱半导体形成的第二栅绝缘层和第二栅极形成在所述第二栅极绝缘层周围的电极，以及至少所述第一选择栅极晶体管或所述第二选择栅极晶体管的沟道区域，所述沟道区域由相对的导电型半导体形成为源极区域和漏极区域。

4. 发明申请

US20110284996A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110284996A1
公开(公告)日：2011-11-24
申请号：US13109086
申请日：2011-05-17
申请人： Takashi Kurusu , Takashi Izumida , Hiroyoshi Tanimoto , Nobutoshi Aoki
发明人： Takashi Kurusu , Takashi Izumida , Hiroyoshi Tanimoto , Nobutoshi Aoki
IPC分类号： H01L23/58 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76838 , H01L23/528 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.
摘要翻译：在一个实施例中，半导体器件包括衬底和设置在衬底上方的相同互连层中的多个互连。该装置还包括多个绝缘体，其设置成埋在多个互连件之间。此外，多个互连包括互连组，其中连续排列2N个或更多个互连，使得各互连的两个侧表面之间的线边缘粗糙度（LER）的相关系数为正，其中N为4或更大的整数。

5. 发明授权

US08829623B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08829623B2
公开(公告)日：2014-09-09
申请号：US12248483
申请日：2008-10-09
申请人： Nobutoshi Aoki , Takashi Izumida , Masaki Kondo , Fumitaka Arai
发明人： Nobutoshi Aoki , Takashi Izumida , Masaki Kondo , Fumitaka Arai
IPC分类号： H01L27/088 , H01L27/115
CPC分类号： H01L27/11529 , H01L27/11524 , H01L27/11526
摘要： According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.
摘要翻译：根据本发明的一个方面，提供了一种半导体存储器件，包括：半导体衬底，具有：接触区域; 选择栅极区; 和存储单元区域; 形成在所述接触区域中并且具有第一深度的第一元件隔离区; 形成在所述选择栅极区中并具有第二深度的第二元件隔离区; 以及形成在所述存储单元区域中并且具有小于所述第一深度的第三深度的第三元件隔离区域。

6. 发明授权

US08354706B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08354706B2
公开(公告)日：2013-01-15
申请号：US12719193
申请日：2010-03-08
申请人： Takahisa Kanemura , Tomomi Kusaka , Takashi Izumida , Masaki Kondo , Nobutoshi Aoki
发明人： Takahisa Kanemura , Tomomi Kusaka , Takashi Izumida , Masaki Kondo , Nobutoshi Aoki
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , G11C16/0441 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/42324
摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer.
摘要翻译：根据本发明实施例的半导体存储器件包括衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的第一栅极绝缘体，形成在第一栅绝缘体上的第一浮栅，第二栅绝缘体形成在第一浮栅上并用作FN隧穿膜的栅极绝缘体，形成在第二栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的栅极绝缘体，以及形成在栅极绝缘体上的控制栅极所述隔间绝缘体，所述第一和第二浮动栅极中的至少一个包括金属层。

7. 发明授权

US08289782B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08289782B2
公开(公告)日：2012-10-16
申请号：US12719420
申请日：2010-03-08
申请人： Takashi Izumida , Tomomi Kusaka , Masaki Kondo , Nobutoshi Aoki
发明人： Takashi Izumida , Tomomi Kusaka , Masaki Kondo , Nobutoshi Aoki
IPC分类号： G11C16/04
CPC分类号： H01L29/7881 , G11C16/0408 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11531 , H01L29/42332 , H01L29/7887
摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the gate insulator, a first intergate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the first intergate insulator, a second intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the second intergate insulator.
摘要翻译：根据本发明的实施例的半导体存储器件包括：衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的栅极绝缘体，形成在栅极绝缘体上的第一浮栅，第一栅极绝缘体形成在第一浮栅上并用作FN隧道膜，形成在第一栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的第二栅极绝缘体，以及形成在第一浮栅上的控制栅第二隔间绝缘子。

8. 发明授权

US08134203B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08134203B2
公开(公告)日：2012-03-13
申请号：US12618119
申请日：2009-11-13
申请人： Takashi Izumida , Nobutoshi Aoki
发明人： Takashi Izumida , Nobutoshi Aoki
IPC分类号： H01L29/788 , H01L29/423
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/0688 , H01L27/11578 , H01L27/11582
摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.
摘要翻译：在设置有沿方向排列的存储单元晶体管和选择晶体管以选择存储单元晶体管的非易失性半导体存储器件中，电荷陷阱型的每个存储单元晶体管至少由第一绝缘层和第一栅极电极，并且选择晶体管至少由第二绝缘层和第二栅电极组成。第一栅电极设置有形成在第一绝缘层上的第一宽度的第一硅化物层。第二栅电极设置有形成在第二绝缘层上的杂质掺杂硅层，以及形成在杂质掺杂硅层上的第二宽度的第二硅化物层。第二硅化物具有与第一硅化物相同的组成。第二宽度大于第一宽度。

9. 发明授权

US07989856B2 Fin transistor 有权
标题翻译：鳍晶体管
公开(公告)号：US07989856B2
公开(公告)日：2011-08-02
申请号：US12335701
申请日：2008-12-16
申请人： Masakazu Goto , Nobutoshi Aoki , Takashi Izumida , Kimitoshi Okano , Satoshi Inaba , Ichiro Mizushima
发明人： Masakazu Goto , Nobutoshi Aoki , Takashi Izumida , Kimitoshi Okano , Satoshi Inaba , Ichiro Mizushima
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/7845
摘要： A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.
摘要翻译：翅片晶体管包括：衬底; 形成在所述基板上的多个半导体翅片; 覆盖半导体鳍片的沟道区域的栅电极; 以及作为用于包括在栅极电极的区域中的半导体鳍片的应力源的构件和设置在半导体鳍片之间的区域，并且该构件由与栅电极不同的材料制成。

10. 发明申请

US20070210355A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070210355A1
公开(公告)日：2007-09-13
申请号：US11713803
申请日：2007-03-05
申请人： Takashi Izumida
发明人： Takashi Izumida
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/6659 , H01L29/7843
摘要： A semiconductor device includes: an insulating layer; a semiconductor fin protruding from the insulating layer, extending in a first direction parallel to a major surface of the insulating layer, and having a source region, a channel section, and a drain region arranged in the first direction; a gate electrode opposed at least to a side face of the channel section in the semiconductor fin and extending in a second direction that is substantially orthogonal to the first direction and parallel to the major surface of the insulating layer; an insulating film interposed between the semiconductor fin and the gate electrode; a spacer layer provided on the channel section; a sidewall insulating layer provided adjacent to a side face of the spacer layer substantially parallel to the second direction; and a stress liner. The stress liner covers the sidewall insulating layer and the spacer layer and has an intrinsic stress for distorting the semiconductor fin. The sidewall insulating layer has a thickness of 45 nanometers (nm) or more in the first direction, and the spacer layer has a height of 105 nanometers (nm) or more.
摘要翻译：半导体器件包括：绝缘层; 从所述绝缘层突出的半导体鳍片，沿着与所述绝缘层的主表面平行的第一方向延伸，并且具有沿所述第一方向排列的源极区域，沟道部分和漏极区域; 至少与所述半导体鳍片中的沟道部分的侧面相对且在与所述第一方向大致正交且平行于所述绝缘层的主表面的第二方向上延伸的栅电极; 介于所述半导体鳍片和所述栅电极之间的绝缘膜; 间隔层，设置在通道部分上; 侧壁绝缘层，设置成与所述间隔层的与所述第二方向大致平行的侧面相邻; 和应力衬垫。应力衬垫覆盖侧壁绝缘层和间隔层，并且具有使半导体翅片变形的固有应力。侧壁绝缘层在第一方向上具有45纳米（nm）以上的厚度，间隔层的高度为105纳米（nm）以上。

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