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    • 4. 发明授权
    • Semiconductor storage device
    • 半导体存储设备
    • US08212306B2
    • 2012-07-03
    • US12721757
    • 2010-03-11
    • Takashi IzumidaNobutoshi AokiMasaki KondoTakahisa Kanemura
    • Takashi IzumidaNobutoshi AokiMasaki KondoTakahisa Kanemura
    • H01L29/788
    • H01L21/28273H01L27/11521H01L29/42324H01L29/66825H01L29/7883
    • A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.
    • 半导体存储装置具有半导体基板,在半导体基板上形成有规定间隔的多个第一绝缘膜,在第一方向上形成在第一绝缘膜之间的元件隔离区域,包括第一电荷累积膜的浮栅电极 形成在所述第一绝缘膜上的第二电荷累积膜,形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜,以及形成的第三电荷累积膜 在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度,形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜, 形成在电荷累积膜上的第三绝缘膜 和沿着第二方向的元件隔离区域,以及形成在第三绝缘膜上的控制栅极电极。
    • 5. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    • 非易失性半导体存储器件
    • US20100207187A1
    • 2010-08-19
    • US12644821
    • 2009-12-22
    • Nobutoshi AokiMasaki KondoTakashi Izumida
    • Nobutoshi AokiMasaki KondoTakashi Izumida
    • H01L29/788
    • H01L27/11521H01L29/40114
    • A nonvolatile semiconductor memory device comprises a memory cell. The memory cell includes a first gate insulating film formed on a semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film. The floating gate includes a first semiconductor film which contacts the first gate insulating film, and a metal film stacked on the semiconductor film. An effective tunneling thickness between the semiconductor substrate and the floating gate in a read operation is thicker than an effective tunneling thickness between the semiconductor substrate and the floating in a write operation.
    • 非易失性半导体存储器件包括存储器单元。 存储单元包括形成在半导体衬底上的第一栅极绝缘膜,形成在第一栅极绝缘膜上的浮置栅极,形成在浮置栅极上的第二栅极绝缘膜,以及形成在第二栅极绝缘膜上的控制栅极。 浮置栅极包括与第一栅极绝缘膜接触的第一半导体膜和层叠在半导体膜上的金属膜。 在读取操作中,半导体衬底和浮置栅极之间的有效隧道厚度比在半导体衬底和写入操作中浮动之间的有效隧穿厚度厚。
    • 7. 发明申请
    • SEMICONDUCTOR STORAGE DEVICE
    • 半导体存储设备
    • US20100295112A1
    • 2010-11-25
    • US12721757
    • 2010-03-11
    • Takashi IzumidaNobutoshi AokiMasaki KondoTakahisa Kanemura
    • Takashi IzumidaNobutoshi AokiMasaki KondoTakahisa Kanemura
    • H01L27/115
    • H01L21/28273H01L27/11521H01L29/42324H01L29/66825H01L29/7883
    • A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.
    • 半导体存储装置具有半导体基板,在半导体基板上形成有规定间隔的多个第一绝缘膜,在第一方向上形成在第一绝缘膜之间的元件隔离区域,包括第一电荷累积膜的浮栅电极 形成在所述第一绝缘膜上的第二电荷累积膜,形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜,以及形成的第三电荷累积膜 在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度,形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜, 形成在电荷累积膜上的第三绝缘膜 和沿着第二方向的元件隔离区域,以及形成在第三绝缘膜上的控制栅极电极。
    • 8. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME
    • 非易失性半导体存储器件及其制造方法
    • US20080246072A1
    • 2008-10-09
    • US11773721
    • 2007-07-05
    • Masaki KondoTakashi IzumidaNobutoshi AokiToshiharu Watanabe
    • Masaki KondoTakashi IzumidaNobutoshi AokiToshiharu Watanabe
    • H01L29/788
    • H01L27/115H01L27/11521H01L27/11524
    • In a nonvolatile semiconductor memory device including a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on the semiconductor substrate and connected between one end of the memory cell column and a common source line, and a second selection transistor formed on the semiconductor substrate and connected between the other end of the memory cell column and a bit line, a recessed portion is formed on a surface of the semiconductor substrate between the first selection transistor and a memory cell adjacent to the first selection transistor, and an edge at a side of the first selection transistor in the recessed portion reaches an end portion at a side of the memory cell in a gate of the first selection transistor.
    • 在包括存储单元列的非易失性半导体存储器件中,该存储单元列是通过串联连接多个存储单元而形成的,每个存储单元具有通过绝缘层在半导体衬底上层叠电荷存储层和控制栅极的结构,第一选择 形成在半导体衬底上并连接在存储单元列的一端和公共源极线之间的晶体管,以及形成在半导体衬底上并连接在存储单元列的另一端和位线之间的第二选择晶体管, 部分形成在第一选择晶体管和与第一选择晶体管相邻的存储单元之间的半导体衬底的表面上,并且凹陷部分中的第一选择晶体管的一侧的边缘到达第二选择晶体管的一侧的端部 第一选择晶体管的栅极中的存储单元。