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1. 发明授权

US5920558A ATM switch and ATM switching system 失效
标题翻译： ATM交换机和ATM交换系统
公开(公告)号：US5920558A
公开(公告)日：1999-07-06
申请号：US829428
申请日：1997-03-31
申请人： Toshitada Saito , Jun Hasegawa , Masahiro Okada , Toshio Fujisawa
发明人： Toshitada Saito , Jun Hasegawa , Masahiro Okada , Toshio Fujisawa
IPC分类号： H04Q3/00 , H04L12/70 , H04J3/22 , H04L12/50
CPC分类号： H04L49/3009 , H04L12/5601 , H04L49/503 , H04L49/3018 , H04L49/3027
摘要： A switch executes complex protocol processing on control cells easily at a high speed in the same manner as normal cells are processed. The switch flexibly copes with new or modifies specifications and standards which might be established in the future for processing RM and OAM cells. Each link interface portion 1 of the ATM switch includes an input cells processing portion 7 and an output cell processing portion 8 provided at the input side and output side of a cell exchange portion 2, and cooperates with a control information maintenance portion 9 to execute application of switching information that the cell exchange portion 2 requires in input cells, and rewriting of ATM cell headers of input cells to and output cells from the cell exchange portion 2. The input cell processing portion 7 and the output cell processing portion 8 of each include a fixed sequencer and a microcode sequencer to execute complex protocol processing such as OAM, RM and other control functions in the microcode sequencer.
摘要翻译：交换机以与正常小区处理相同的方式高速地容易地对控制小区执行复杂的协议处理。该交换机灵活应对新的或修改将来可能建立的用于处理RM和OAM信元的规范和标准。 ATM交换机的每个链路接口部分1包括设置在小区交换部分2的输入侧和输出侧的输入小区处理部分7和输出小区处理部分8，并与控制信息维护部分9协作以执行应用在单元交换部分2需要输入单元的切换信息，以及将输入单元的ATM信元头部重写到单元交换部分2并从单元交换部分2输出单元。每个输入单元处理部分7和输出单元处理部分8包括一个固定的音序器和一个微码序列器来执行诸如OAM，RM和微码序列器中的其他控制功能的复杂的协议处理。

2. 发明授权

US06434675B1 Method and apparatus for updating data stored in plural storage means in an information processing system 有权
公开(公告)号：US06434675B1
公开(公告)日：2002-08-13
申请号：US09785003
申请日：2001-02-15
申请人： Jun Hasegawa , Toshitada Saito , Masahiro Okada , Toshio Fujisawa
发明人： Jun Hasegawa , Toshitada Saito , Masahiro Okada , Toshio Fujisawa
IPC分类号： G06F1212
摘要： A storage means control apparatus of this invention includes a first processing unit for performing write processing in a first storage unit, a second processing unit for performing write processing in a second storage unit, a tag data control unit for managing tag data representing storage areas where the first processing unit has performed write processing in the first storage unit (101), another tag data control unit for managing another tag data representing storage areas where the second processing unit has performed write processing in the second storage unit, a priority data control unit for managing priority data representing a priority of each of the first and second processing units in units of storage areas of the second storage unit, a prevention data control unit for managing prevention data for preventing write processing in each storage area of the second storage unit using the priority data and the tag data, and a processing data updating unit for writing the data written in the first storage unit (101) in the second storage unit on the basis of the prevention data. With this arrangement, when each write control unit in a plurality of processing units performs write processing in the storage unit of the self processing unit, matching of stored contents among the units can be ensured.

3. 发明授权

US06219762B1 Method and apparatus for assigning priority to update data stored in plural storage means 失效
标题翻译：用于分配优先级以更新存储在多个存储装置中的数据的方法和装置
公开(公告)号：US06219762B1
公开(公告)日：2001-04-17
申请号：US08892490
申请日：1997-07-14
申请人： Jun Hasegawa , Toshitada Saito , Masahiro Okada , Toshio Fujisawa
发明人： Jun Hasegawa , Toshitada Saito , Masahiro Okada , Toshio Fujisawa
IPC分类号： G06F1318
CPC分类号： G06F12/0817
摘要： A storage means control apparatus of this invention includes a first processing unit for performing write processing in a first storage unit, a second processing unit for performing write processing in a second storage unit, a revealing data control unit for managing revealing data representing storage areas where the first processing unit has performed write processing in the first storage unit (101), another revealing data control unit for managing another revealing data representing storage areas where the second processing unit has performed write processing in the second storage unit, a priority data control unit for managing priority data representing a priority of each of the first and second processing units in units of storage areas of the second storage unit, a inhibition data control unit for managing inhibition data for inhibiting write processing in each storage area of the second storage unit using the priority data and the revealing data, and a processing data reflection unit for writing the data written in the first storage unit (101) in the second storage unit on the basis of the inhibition data. With this arrangement, when each write control unit in a plurality of processing units performs write processing in the storage unit of the self processing unit, matching of stored contents among the units can be ensured.
摘要翻译：本发明的存储装置控制装置包括用于在第一存储单元中执行写入处理的第一处理单元，用于在第二存储单元中执行写入处理的第二处理单元，用于管理表示存储区域的显示数据的显示数据控制单元，第一处理单元在第一存储单元（101）中执行写入处理，另一个显示数据控制单元，用于管理表示第二处理单元在第二存储单元中执行写入处理的存储区域的另一显示数据，优先级数据控制单元用于以第二存储单元的存储区域为单位管理表示第一处理单元和第二处理单元的优先级的优先级数据;禁止数据控制单元，用于管理用于禁止第二存储单元的每个存储区域中的写入处理的禁止数据，所述禁止数据使用优先级数据和显示数据，以及处理数据反映单元，用于基于禁止数据写入写入第二存储单元中的第一存储单元（101）中的数据。利用这种布置，当多个处理单元中的每个写入控制单元在自身处理单元的存储单元中执行写入处理时，可以确保各单元之间存储的内容的匹配。

4. 发明授权

US06198742B1 ATM switching system 失效
标题翻译： ATM交换系统
公开(公告)号：US06198742B1
公开(公告)日：2001-03-06
申请号：US08972064
申请日：1997-11-17
申请人： Toshitada Saito , Jun Hasegawa , Toshio Fujisawa
发明人： Toshitada Saito , Jun Hasegawa , Toshio Fujisawa
IPC分类号： H04L1228
CPC分类号： H04L12/5601
摘要： An input cell processing portion 11 and an output cell processing portion 12 in a line interface 10 execute a normal ATM process and an insertion/divergence process etc with respect to an input cell flow and an output cell flow. A cell buffer 40 is constructed on an external memory device to accumulate a template (format) of ATM cells to be processed. The input cell processing portion 11 or the output cell processing unit 12 in the line interface 10 judges whether a necessity for inserting the network management cell might arise or not when processing the input cell flow. Upon detecting herein that the insertion necessity arises, the management cell template previously held on the cell buffer 40 is read, and, after a necessary data replacing process has been executed thereon, the management cell is inserted into the input cell flow or the output cell flow.
摘要翻译：行界面10中的输入单元处理部11和输出单元处理部12相对于输入单元流和输出单元流执行通常的ATM处理和插入/发散处理等。单元缓冲器40构造在外部存储器件上以累积要处理的ATM单元的模板（格式）。线路接口10中的输入单元处理部分11或输出单元处理单元12判断在处理输入单元流时是否可能出现插入网络管理单元的必要性。在检测到插入的必要性出现时，先前保持在单元缓冲器40上的管理单元模板被读取，并且在执行必要的数据替换处理之后，将管理单元插入到输入单元流或输出单元流。

5. 发明授权

US06785290B1 Line interface integrated circuit and packet switch 失效
标题翻译：线路接口集成电路和分组交换机
公开(公告)号：US06785290B1
公开(公告)日：2004-08-31
申请号：US09694792
申请日：2000-10-24
申请人： Toshio Fujisawa , Toshitada Saito , Jun Hasegawa
发明人： Toshio Fujisawa , Toshitada Saito , Jun Hasegawa
IPC分类号： H04L1228
CPC分类号： H04L49/3081 , H04L49/25 , H04L49/30 , H04L2012/5625 , H04L2012/5651 , H04L2012/5679
摘要： ATM cells inputted into a physical layer interface (12) are once stored in a cell buffer (24) regardless whether they are ATM cells to be outputted from a switching interface (22) or ATM cells addressed to host CPU (26), and the ATM cells addressed to the host CPU are stored in a temporary RAM (18) at a timing controlled by a scheduler (16). The host CPU 26 read out ATM cells stored in the temporary RAM (18) when necessary. Thereby, no FIFO memory is needed to temporarily store ATM cells addressed to the host CPU (26).
摘要翻译：输入到物理层接口（12）的ATM信元一旦被存储在信元缓冲器（24）中，无论它们是否是从切换接口（22）输出的ATM信元或者寻址到主机CPU（26）的ATM信元，寻址到主机CPU的ATM信元在由调度器（16）控制的定时存储在临时RAM（18）中。当需要时，主机CPU26读出存储在临时RAM（18）中的ATM信元。因此，不需要FIFO存储器来临时存储寻址到主机CPU（26）的ATM信元。

6. 发明授权

US08065486B2 Cache memory control circuit and processor 有权
标题翻译：高速缓存存储器控制电路和处理器
公开(公告)号：US08065486B2
公开(公告)日：2011-11-22
申请号：US12400308
申请日：2009-03-09
申请人： Toshio Fujisawa
发明人： Toshio Fujisawa
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F2212/502 , Y02D10/13
摘要： A cache memory control circuit includes a selecting section configured to be capable of selecting, in a predetermined order, each way or a predetermined two or more ways of a cache memory having multiple ways; a comparing section configured to detect a cache hit in each way; and a control section configured to, upon detection of a cache hit, stop a selection of the respective ways or the predetermined two or more ways at the selecting section.
摘要翻译：高速缓冲存储器控制电路包括：选择部分，被配置为能够以预定顺序选择具有多种方式的高速缓冲存储器的每一路或预定的两个或更多路; 比较部，被配置为以各种方式检测高速缓存命中; 以及控制部，被配置为在检测到高速缓存命中时，在所述选择部分停止对各个方式的选择或所述预定的两个或多个方式。

7. 发明授权

US07808293B2 Clock distribution circuit 有权
标题翻译：时钟分配电路
公开(公告)号：US07808293B2
公开(公告)日：2010-10-05
申请号：US12399463
申请日：2009-03-06
申请人： Toshio Fujisawa
发明人： Toshio Fujisawa
IPC分类号： G06F1/04 , H03H11/26
CPC分类号： H03H11/26 , G06F1/04
摘要： A clock distribution circuit includes a monitoring circuit that delays a signal based on a clock signal from a clock tree by using multiple inverter circuits and predicts a timing violation on the basis of the amount of delay produced by the multiple inverter circuits. The clock distribution circuit further includes an OR circuit that controls, on the basis of the result of prediction by the monitoring circuit, a clock gating signal generated by a combinational circuit and a clock gating circuit that supplies a clock signal or stops supply of the clock signal depending on a signal output from the OR circuit.
摘要翻译：时钟分配电路包括监控电路，其通过使用多个反相器电路基于来自时钟树的时钟信号来延迟信号，并且基于由多个反相器电路产生的延迟量来预测定时违反。时钟分配电路还包括OR电路，其根据监视电路的预测结果控制由组合电路产生的时钟选通信号和提供时钟信号的时钟门控电路或停止提供时钟信号取决于从OR电路输出的信号。

8. 发明申请

US20090224812A1 CLOCK DISTRIBUTION CIRCUIT 有权
标题翻译：时钟分配电路
公开(公告)号：US20090224812A1
公开(公告)日：2009-09-10
申请号：US12399463
申请日：2009-03-06
申请人： Toshio Fujisawa
发明人： Toshio Fujisawa
IPC分类号： H03H11/26
CPC分类号： H03H11/26 , G06F1/04
摘要： A clock distribution circuit includes a monitoring circuit that delays a signal based on a clock signal from a clock tree by using multiple inverter circuits and predicts a timing violation on the basis of the amount of delay produced by the multiple inverter circuits. The clock distribution circuit further includes an OR circuit that controls, on the basis of the result of prediction by the monitoring circuit, a clock gating signal generated by a combinational circuit and a clock gating circuit that supplies a clock signal or stops supply of the clock signal depending on a signal output from the OR circuit.
摘要翻译：时钟分配电路包括监控电路，其通过使用多个反相器电路基于来自时钟树的时钟信号来延迟信号，并且基于由多个反相器电路产生的延迟量来预测定时违反。时钟分配电路还包括OR电路，其根据监视电路的预测结果控制由组合电路产生的时钟选通信号和提供时钟信号的时钟门控电路或停止提供时钟信号取决于从OR电路输出的信号。

9. 发明授权

US08312232B2 Cache memory control circuit and processor for selecting ways in which a cache memory in which the ways have been divided by a predeterminded division number 有权
标题翻译：高速缓冲存储器控制电路和处理器，用于选择其中方式被预先划分的划分数除以高速缓冲存储器的方式
公开(公告)号：US08312232B2
公开(公告)日：2012-11-13
申请号：US12483445
申请日：2009-06-12
申请人： Toshio Fujisawa
发明人： Toshio Fujisawa
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0864 , Y02D10/13
摘要： A cache memory control circuit includes a selecting section configured to select each way or two or more ways in a cache memory in which plural ways have been divided by a predetermined division number, in a predetermined order; a detecting section configured to detect a cache hit in each way; a controlling section configured to, if the cache hit is detected, stop the selection of each way in the selecting section; and a division number changing section having a comparing section, which compares respective values of two pieces of read data from the cache memory having been propagated through two paths, one of which has a predetermined amount of delay with respect to the other one, the division number changing section which changes the predetermined division number depending on whether the two pieces of the read data match or mismatch with each other in the comparing section.
摘要翻译：高速缓冲存储器控制电路包括：选择部，被配置为以预定顺序在多路中以预定分割数划分的高速缓冲存储器中的每一路或两路或多条路; 检测部，被配置为以各路检测高速缓存命中; 控制部，被配置为，如果检测到所述高速缓存命中，则停止所述选择部中的每个路径的选择; 以及分割数变更部，具有比较部，其比较来自已经通过两条路径传播的高速缓冲存储器的两条读取数据的相应值，其中一条相对于另一条路径具有预定的延迟量，数字变更部，其根据所述两个读取数据在所述比较部中是否匹配或不匹配而改变所述预定分割数。

10. 发明授权

US08552784B2 Semiconductor integrated circuit for generating clock signal(s) 失效
标题翻译：用于产生时钟信号的半导体集成电路
公开(公告)号：US08552784B2
公开(公告)日：2013-10-08
申请号：US13235615
申请日：2011-09-19
申请人： Toshio Fujisawa , Hideo Kasami
发明人： Toshio Fujisawa , Hideo Kasami
IPC分类号： G06F1/04 , H03K3/00 , H03K3/013
CPC分类号： H03K5/05 , H03K3/012
摘要： A semiconductor integrated circuit according to an embodiment includes a clock signal generation section, a clock waveform shaping section and a plurality of function blocks. The clock signal generation section generates a clock signal of a predetermined frequency. The clock waveform shaping section generates a plurality of clock signals having the same phase as a phase of the clock signal generated by the clock signal generation section at rising edges and different phases at falling edges. Each of the plurality of function blocks has a plurality of flip flops that operate with any one of the plurality of clock signals generated by the clock waveform shaping section.
摘要翻译：根据实施例的半导体集成电路包括时钟信号产生部分，时钟波形整形部分和多个功能块。时钟信号生成部生成预定频率的时钟信号。时钟波形整形部分产生与时钟信号产生部分在上升沿产生的时钟信号的相位相同的相位的多个时钟信号，并且在下降沿产生不同的相位。多个功能块中的每一个具有多个触发器，它们由时钟波形整形部分产生的多个时钟信号中的任何一个操作。

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