专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08587336B2 Reconfigurable logic block, programmable logic device provided with the reconfigurable logic block, and method of fabricating the reconfigurable logic block 失效
标题翻译：可配置逻辑块，可配置逻辑块的可编程逻辑器件，以及制造可重构逻辑块的方法
公开(公告)号：US08587336B2
公开(公告)日：2013-11-19
申请号：US11598679
申请日：2006-11-14
申请人： Toshinori Sueyoshi , Masahiro Iida , Motoki Amagasaki , Kazuhiko Taketa , Taketo Heishi , Nobuharu Suzuki
发明人： Toshinori Sueyoshi , Masahiro Iida , Motoki Amagasaki , Kazuhiko Taketa , Taketo Heishi , Nobuharu Suzuki
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , H03K19/17728
摘要： A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.
摘要翻译：可重配置逻辑块具有配置运算电路的第一电路和将运算电路外部的电路配置的第二电路。通过改变第一和第二电路中的预定信号的设置来配置多个不同的电路。

2. 发明申请

US20070186203A1 Reconfigurable logic block, programmable logic device provided with the reconfigurable logic block, and method of fabricating the reconfigurable logic block 失效
标题翻译：可配置逻辑块，可配置逻辑块的可编程逻辑器件，以及制造可重构逻辑块的方法
公开(公告)号：US20070186203A1
公开(公告)日：2007-08-09
申请号：US11598679
申请日：2006-11-14
申请人： Toshinori Sueyoshi , Masahiro Iida , Motoki Amagasaki , Kazuhiko Taketa , Taketo Heishi , Nobuharu Suzuki
发明人： Toshinori Sueyoshi , Masahiro Iida , Motoki Amagasaki , Kazuhiko Taketa , Taketo Heishi , Nobuharu Suzuki
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： H03K19/17748 , H03K19/17728
摘要： A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.
摘要翻译：可重配置逻辑块具有配置运算电路的第一电路和将运算电路外部的电路配置的第二电路。通过改变第一和第二电路中的预定信号的设置来配置多个不同的电路。

3. 再颁专利

USRE45199E1 Compiler apparatus 有权
标题翻译：编译器
公开(公告)号：USRE45199E1
公开(公告)日：2014-10-14
申请号：US13616573
申请日：2012-09-14
申请人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
发明人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/433
摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.
摘要翻译：可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线中间程序，使数据依赖关系发生变化。

4. 发明授权

US08402445B2 Program translation method and notifying instruction inserting method 有权
标题翻译：程序翻译方法和通知指令插入方法
公开(公告)号：US08402445B2
公开(公告)日：2013-03-19
申请号：US12962075
申请日：2010-12-07
申请人： Yoko Makiyori , Taketo Heishi , Akira Takuma
发明人： Yoko Makiyori , Taketo Heishi , Akira Takuma
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/41
摘要： The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions. According to this, the present invention enables analysis of the executed range in the program that includes the conditional instructions as well.
摘要翻译：本发明包括：转换步骤，用于将源程序转换为机器语言程序; 插入步骤，用于插入用于通知在程序语言程序中执行源程序的通知指令; 以及程序生成步骤，用于从其中插入通知指令的机器语言程序生成可执行程序。此外，在插入步骤中，通知指令被放置在构成机器语言程序的每个基本块的入口点，并且与条件指令组的条件相同的通知指令被放置在入口点的机器语言程序中提供的条件指令组。在程序生成步骤中，向通知指示的每一个授予用于识别通知指令的识别信息。据此，本发明还能够对包括条件指令的程序中的执行范围进行分析。

5. 发明授权

US08286145B2 Program re-writing apparatus 有权
标题翻译：程序重写装置
公开(公告)号：US08286145B2
公开(公告)日：2012-10-09
申请号：US12107450
申请日：2008-04-22
申请人： Teruo Kawabata , Masatsugu Daimon , Taketo Heishi , Hajime Ogawa
发明人： Teruo Kawabata , Masatsugu Daimon , Taketo Heishi , Hajime Ogawa
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： A program re-writing method which re-writes an inputted program into a program for a processor for controlling whether or not a process is executed based on a yes or no execution flag, said program re-writing method including: inserting a comparison process into the inputted program, the comparison process comparing first address information, which is memory address information accessed by a first memory access process included in the inputted program, and second address information, which is address information of a memory accessed by a second memory access process included in the inputted program, and writing a comparison result into the yes or no execution flag; and inserting a yes or no execution flag-attached logic preservation process into the inputted program, the yes or no execution flag-attached logic preservation process being a process executed based on a value of the yes or no execution flag and preserving the same result as a result of the inputted program when executed.
摘要翻译：一种程序重写方法，其将输入的程序重写到用于处理器的程序中，用于基于是或否执行标志来控制是否执行处理，所述程序重写方法包括：将比较处理插入到所输入的程序，比较第一地址信息的比较处理，第一地址信息是由包括在输入的程序中的第一存储器访问处理访问的存储器地址信息和作为包括第二存储器访问处理访问的存储器的地址信息的第二地址信息在输入的程序中，将比较结果写入是或否执行标志; 并且在输入的程序中插入“是”或“否”执行标志附加的逻辑保存处理，“是”或“否”执行标志附加的逻辑保存处理是基于“是”或“否”执行标志的值执行的处理，并且保持与执行时输入程序的结果。

6. 发明授权

US07856629B2 Compiler apparatus 有权
标题翻译：编译器
公开(公告)号：US07856629B2
公开(公告)日：2010-12-21
申请号：US11420059
申请日：2006-05-24
申请人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
发明人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/433
摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.
摘要翻译：可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线中间程序，使数据依赖关系发生变化。

7. 发明授权

US07185324B2 Compiler apparatus and method for determining locations for data in memory area 有权
标题翻译：用于确定存储器区域中的数据的位置的编译器装置和方法
公开(公告)号：US07185324B2
公开(公告)日：2007-02-27
申请号：US10631960
申请日：2003-08-01
申请人： Shohei Michimoto , Hajime Ogawa , Toshiyuki Sakata , Taketo Heishi , Shuichi Takayama
发明人： Shohei Michimoto , Hajime Ogawa , Toshiyuki Sakata , Taketo Heishi , Shuichi Takayama
IPC分类号： G06F9/45 , G06F12/00 , G06F12/02
CPC分类号： G06F9/5016 , G06F8/443 , G06F9/44557
摘要： Disclosed is a compiler apparatus for generating an instruction code composed of instruction sets each including an instruction that designates an m-bit immediate value indicating a location of a data item in a memory area. The compiler apparatus sequentially selects, based on one data attribute, a data item from a group X composed of a plurality of data items; and judges, each time a data item is selected, whether the selected data item is allocatable to an n-byte memory area (n≦2m). When the judgment is negative, the compiler apparatus specifies, based on a different data attribute, a data item out of all the selected data items and excludes the specified data item from the group X, and repeats the selection until all the data items remaining in the group X after excluding specified data items are judged to be allocatable to the memory area.
摘要翻译：公开了一种编译装置，用于生成由指令集构成的指令代码，每个指令集包括指定指示存储区中的数据项的位置的m位立即值的指令。编译装置根据一个数据属性从由多个数据项组成的组X中依次选择数据项; 并且每当选择数据项时，判断所选择的数据项是否可分配给n字节存储区（n <= 2 ^{m）。当判断为否定时，编译装置根据不同的数据属性指定所有选择的数据项中的数据项，并从组X中排除指定的数据项，并重复选择，直到剩余的所有数据项在排除指定数据项之后的组X被判断为可分配给存储区。}

8. 发明授权

US06880150B1 PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND A DISASSEMBLER FOR SUCH PROCESSOR 有权
标题翻译：执行单元中指令的处理程序，与指令读取的单元相关，以及编译器，优化设备，汇编器，链接器，调试器和此类处理器的分解器
公开(公告)号：US06880150B1
公开(公告)日：2005-04-12
申请号：US09301284
申请日：1999-04-28
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当指令解码器409a〜409c解码分支指令时，分支指令中包含的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

9. 发明申请

US20050010897A1 Program generating apparatus 审中-公开
标题翻译：程序生成装置
公开(公告)号：US20050010897A1
公开(公告)日：2005-01-13
申请号：US10880523
申请日：2004-07-01
申请人： Hajime Ogawa , Taketo Heishi , Shuichi Takayama , Chen Zhao
发明人： Hajime Ogawa , Taketo Heishi , Shuichi Takayama , Chen Zhao
IPC分类号： G06F11/28 , G06F9/44
CPC分类号： G06F8/30 , G06F8/43 , G06F8/51
摘要： A test program generating apparatus for a compiler comprising: a conditional expression generating unit operable to receive a description of a control structure of a program and generate a plurality of conditional expressions to be inserted into insert parts of the conditional expressions of the control structure using a linear programming method, the plurality of conditional expressions allowing a control flow of the program to pass through all paths in the control structure; an initial value generating unit operable to generate initial values of variables, for each of all the paths, which are included in the plurality of conditional expressions for allowing the control flow of the program to pass through all the paths in the control structure; and a test program generating unit operable to generate a test program based on the control structure, the conditional expressions and the initial values.
摘要翻译：一种用于编译器的测试程序生成装置，包括：条件表达式生成单元，用于接收对程序的控制结构的描述，并生成多个条件表达式，以使用以下操作插入到控制结构的条件表达式的插入部分中所述多个条件表达式允许所述程序的控制流程通过所述控制结构中的所有路径; 初始值生成单元，用于针对包含在所述多个条件表达式中的每个所述路径生成用于允许所述程序的控制流通过所述控制结构中的所有路径的变量的初始值; 以及测试程序生成单元，其可操作以基于所述控制结构，所述条件表达式和所述初始值生成测试程序。

10. 发明授权

US06820223B2 Processor, compiling apparatus, and compile program recorded on a recording medium 有权
标题翻译：处理器，编译装置和编译程序记录在记录介质上
公开(公告)号：US06820223B2
公开(公告)日：2004-11-16
申请号：US10306330
申请日：2002-11-27
申请人： Taketo Heishi , Kensuke Odani
发明人： Taketo Heishi , Kensuke Odani
IPC分类号： G06F1100
CPC分类号： G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3838 , G06F9/3853
摘要： Each of registers R0 to R31 is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit 431 outputs information to the selectors 4321 and 4322 on the registers and the locations (upper and lower areas) in which data is written by the instructions that have issued in one cycle. Each of the selectors 4321 and 4322 selects one out of pieces of data that have been output from first, second, and third arithmetic operation units 44, 45, and 46 and writes the selected data in the upper or lower area in one register. A dependency analysis unit 110 in a compiling apparatus considers the upper and lower registers in one 64-bit register as separate resources, analyzes the data dependency relations between the instructions, and generates a dependency graph that indicates the data dependency relations. A instruction rearrangement unit 111 rearranges the instructions and generates execution codes using the dependency graph.
摘要翻译：每个寄存器R0至R31被划分为上部32位区域和下部32位区域。寄存器写入控制单元431向寄存器上的选择器4321和4322输出信息，并且通过在一个周期中发出的指令来写入数据的位置（上部和下部区域）。选择器4321和4322中的每一个选择从第一，第二和第三算术运算单元44,45和46输出的数据中的一个，并将选择的数据写入一个寄存器的上部或下部区域。编译装置中的依赖关系分析单元110将一个64位寄存器中的上下寄存器视为单独的资源，分析指令之间的数据依赖关系，并生成指示数据依赖关系的依赖图。指令重排单元111重新排列指令，并使用依赖图生成执行代码。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式