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1. 发明授权

US08286145B2 Program re-writing apparatus 有权
标题翻译：程序重写装置
公开(公告)号：US08286145B2
公开(公告)日：2012-10-09
申请号：US12107450
申请日：2008-04-22
申请人： Teruo Kawabata , Masatsugu Daimon , Taketo Heishi , Hajime Ogawa
发明人： Teruo Kawabata , Masatsugu Daimon , Taketo Heishi , Hajime Ogawa
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： A program re-writing method which re-writes an inputted program into a program for a processor for controlling whether or not a process is executed based on a yes or no execution flag, said program re-writing method including: inserting a comparison process into the inputted program, the comparison process comparing first address information, which is memory address information accessed by a first memory access process included in the inputted program, and second address information, which is address information of a memory accessed by a second memory access process included in the inputted program, and writing a comparison result into the yes or no execution flag; and inserting a yes or no execution flag-attached logic preservation process into the inputted program, the yes or no execution flag-attached logic preservation process being a process executed based on a value of the yes or no execution flag and preserving the same result as a result of the inputted program when executed.
摘要翻译：一种程序重写方法，其将输入的程序重写到用于处理器的程序中，用于基于是或否执行标志来控制是否执行处理，所述程序重写方法包括：将比较处理插入到所输入的程序，比较第一地址信息的比较处理，第一地址信息是由包括在输入的程序中的第一存储器访问处理访问的存储器地址信息和作为包括第二存储器访问处理访问的存储器的地址信息的第二地址信息在输入的程序中，将比较结果写入是或否执行标志; 并且在输入的程序中插入“是”或“否”执行标志附加的逻辑保存处理，“是”或“否”执行标志附加的逻辑保存处理是基于“是”或“否”执行标志的值执行的处理，并且保持与执行时输入程序的结果。

2. 发明授权

US07571432B2 Compiler apparatus for optimizing high-level language programs using directives 有权
标题翻译：用于使用指令优化高级语言程序的编译器设备
公开(公告)号：US07571432B2
公开(公告)日：2009-08-04
申请号：US10944831
申请日：2004-09-21
申请人： Taketo Heishi , Hajime Ogawa , Yasuhiro Yamamoto , Kyoko Hattori , Shohei Michimoto , Kenji Hattori , Hirotetsu Tomita , Teruo Kawabata , Kiyoshi Nakashima
发明人： Taketo Heishi , Hajime Ogawa , Yasuhiro Yamamoto , Kyoko Hattori , Shohei Michimoto , Kenji Hattori , Hirotetsu Tomita , Teruo Kawabata , Kiyoshi Nakashima
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.
摘要翻译：编译器58是以较少的工时实现程序开发的编译器，将以高级语言编写的源程序72翻译成机器语言程序。该编译器58包括：指令获取单元，其获得应当优化要生成的机器语言程序的指令; 解析源程序72的解析器单元76; 中间代码转换单元78，其基于由解析器单元76执行的解析的结果将源程序72转换为中间代码; 优化单元68，根据该指令优化中间代码; 以及将中间代码转换为机器语言程序的代码生成单元90。上述指令是优化针对使用高速缓存的处理器的机器语言程序的指令。

3. 发明申请

US20050086653A1 Compiler apparatus 有权
标题翻译：编译器
公开(公告)号：US20050086653A1
公开(公告)日：2005-04-21
申请号：US10944831
申请日：2004-09-21
申请人： Taketo Heishi , Hajime Ogawa , Yasuhiro Yamamoto , Kyoko Hattori , Shohei Michimoto , Kenji Hattori , Hirotetsu Tomita , Teruo Kawabata , Kiyoshi Nakashima
发明人： Taketo Heishi , Hajime Ogawa , Yasuhiro Yamamoto , Kyoko Hattori , Shohei Michimoto , Kenji Hattori , Hirotetsu Tomita , Teruo Kawabata , Kiyoshi Nakashima
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.
摘要翻译：编译器58是以较少的工时实现程序开发的编译器，将以高级语言编写的源程序72翻译成机器语言程序。该编译器58包括：指令获取单元，其获得应当优化要生成的机器语言程序的指令; 解析源程序72的解析器单元76; 中间代码转换单元78，其基于由解析器单元76执行的解析的结果将源程序72转换为中间代码; 优化单元68，根据该指令优化中间代码; 以及将中间代码转换为机器语言程序的代码生成单元90。上述指令是优化针对使用高速缓存的处理器的机器语言程序的指令。

4. 再颁专利

USRE45199E1 Compiler apparatus 有权
标题翻译：编译器
公开(公告)号：USRE45199E1
公开(公告)日：2014-10-14
申请号：US13616573
申请日：2012-09-14
申请人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
发明人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/433
摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.
摘要翻译：可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线中间程序，使数据依赖关系发生变化。

5. 发明授权

US07856629B2 Compiler apparatus 有权
标题翻译：编译器
公开(公告)号：US07856629B2
公开(公告)日：2010-12-21
申请号：US11420059
申请日：2006-05-24
申请人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
发明人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/433
摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.
摘要翻译：可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线中间程序，使数据依赖关系发生变化。

6. 发明申请

US20060248520A1 Program conversion device and program conversion method 审中-公开
标题翻译：程序转换装置和程序转换方法
公开(公告)号：US20060248520A1
公开(公告)日：2006-11-02
申请号：US10565530
申请日：2005-02-04
申请人： Teruo Kawabata , Hajime Ogawa , Taketo Heishi , Yasuhiro Yamamoto , Shohei Michimoto
发明人： Teruo Kawabata , Hajime Ogawa , Taketo Heishi , Yasuhiro Yamamoto , Shohei Michimoto
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A compiler which improves the processing speed of a program execution without needlessly issuing an instruction that has a possibility of causing an interlock is targeted at a processor having an instruction that has a possibility of causing an interlock when the instruction is executed, the compiler causing a computer to function as: a loop structure transforming unit (186) which performs double looping transformation on an input program so that a loop whose iteration count is y is split off from a loop whose loop count is x and the loop whose iteration count is y is an inner loop whereas a loop whose iteration count is x/y is an outer loop; and an instruction optimum placing unit (187) which places an instruction that has a possibility of causing an interlock in the program on which the double looping transformation has been performed.
摘要翻译：一种改进程序执行的处理速度而不用不必要地发出具有引起互锁的可能性的指令的编译器针对具有在执行指令时可能引起互锁的指令的处理器，编译器引起计算机用作：循环结构变换单元（186），其对输入程序执行双循环变换，使得迭代计数为y的循环与循环计数为x的循环和迭代计数为y的循环分离是一个内循环，而迭代计数为x / y的循环是一个外循环; 以及指令最佳放置单元（187），其放置在执行了双重循环变换的程序中具有引起互锁的可能性的指令。

7. 发明授权

US08612958B2 Program converting apparatus and program conversion method 有权
标题翻译：程序转换装置和程序转换方法
公开(公告)号：US08612958B2
公开(公告)日：2013-12-17
申请号：US13163035
申请日：2011-06-17
申请人： Taketo Heishi , Shohei Michimoto , Teruo Kawabata
发明人： Taketo Heishi , Shohei Michimoto , Teruo Kawabata
IPC分类号： G06F9/45
CPC分类号： G06F8/445 , G06F8/314
摘要： A compiler, which corresponds to a recent processor having a multithread function, that enables execution of efficient instruction scheduling and allows a programmer to control the instruction scheduling includes: an instruction scheduling directive receiving unit which receives, from a programmer, a directive for specifying an instruction scheduling method; and an instruction scheduling unit which executes, conforming to one of instruction scheduling methods, instruction scheduling of rearranging intermediate codes corresponding to the source program. The instruction scheduling unit selects one of instruction scheduling methods according to the directive received by the instruction scheduling directive receiving unit, and executes instruction scheduling conforming to the selected instruction scheduling method.
摘要翻译：一种编译器，其对应于具有多线程功能的最近的处理器，其能够执行有效的指令调度并允许程序员控制指令调度包括：指令调度指令接收单元，其从程序员接收用于指定指令调度方法; 以及指令调度单元，其执行符合指令调度方法之一的重新排列与源程序对应的中间代码的指令调度。指令调度单元根据指令调度指示接收单元接收的指令选择指令调度方法之一，并执行符合所选指令调度方法的指令调度。

8. 发明申请

US20080307177A1 PROGRAM CONVERSION DEVICE 审中-公开
标题翻译：程序转换装置
公开(公告)号：US20080307177A1
公开(公告)日：2008-12-11
申请号：US12105706
申请日：2008-04-18
申请人： Masatsugu Daimon , Naoko Nakahara , Toshiyuki Sakata , Teruo Kawabata
发明人： Masatsugu Daimon , Naoko Nakahara , Toshiyuki Sakata , Teruo Kawabata
IPC分类号： G06F12/02 , G06F12/16 , G06F12/14
CPC分类号： G06F8/443
摘要： An analysis section analyzes the live range of a first variable shared among subroutines and the live range of a second variable used only in a subroutine. The allocation section allocates the second variable in an allocation memory for the first variable if the live ranges of the first and second variables do not overlap each other.
摘要翻译：分析部分分析子程序中共享的第一个变量的生存范围和仅在子程序中使用的第二个变量的生存范围。如果第一和第二变量的生存范围彼此不重叠，则分配部分将第二变量分配给第一变量的分配存储器。

9. 发明申请

US20050216869A1 Compiler 有权
标题翻译：编译器
公开(公告)号：US20050216869A1
公开(公告)日：2005-09-29
申请号：US11087752
申请日：2005-03-24
申请人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
发明人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
IPC分类号： G06F17/50
CPC分类号： G06F8/423 , G06F17/505
摘要： A compiler apparatus enabling description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.
摘要翻译：尽管在硬件设计中输入编程语言的描述是不可能的，但是使用现有编程语言来描述特定硬件模块的编译器装置。在头文件24中，定义了难以形容的编程语言中的特定硬件。并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码硬件。

10. 发明授权

US07350165B2 Compiler 有权
标题翻译：编译器
公开(公告)号：US07350165B2
公开(公告)日：2008-03-25
申请号：US11087752
申请日：2005-03-24
申请人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
发明人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
IPC分类号： G06F17/50
CPC分类号： G06F8/423 , G06F17/505
摘要： A compiler apparatus enables description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.
摘要翻译：编译装置能够描述现有编程语言中的特定硬件模块，尽管在硬件设计中输入编程语言的描述是不可能的。在头文件24中，定义了难以形容的编程语言中的特定硬件。并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码硬件。

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