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1. 发明授权

US07185324B2 Compiler apparatus and method for determining locations for data in memory area 有权
标题翻译：用于确定存储器区域中的数据的位置的编译器装置和方法
公开(公告)号：US07185324B2
公开(公告)日：2007-02-27
申请号：US10631960
申请日：2003-08-01
申请人： Shohei Michimoto , Hajime Ogawa , Toshiyuki Sakata , Taketo Heishi , Shuichi Takayama
发明人： Shohei Michimoto , Hajime Ogawa , Toshiyuki Sakata , Taketo Heishi , Shuichi Takayama
IPC分类号： G06F9/45 , G06F12/00 , G06F12/02
CPC分类号： G06F9/5016 , G06F8/443 , G06F9/44557
摘要： Disclosed is a compiler apparatus for generating an instruction code composed of instruction sets each including an instruction that designates an m-bit immediate value indicating a location of a data item in a memory area. The compiler apparatus sequentially selects, based on one data attribute, a data item from a group X composed of a plurality of data items; and judges, each time a data item is selected, whether the selected data item is allocatable to an n-byte memory area (n≦2m). When the judgment is negative, the compiler apparatus specifies, based on a different data attribute, a data item out of all the selected data items and excludes the specified data item from the group X, and repeats the selection until all the data items remaining in the group X after excluding specified data items are judged to be allocatable to the memory area.
摘要翻译：公开了一种编译装置，用于生成由指令集构成的指令代码，每个指令集包括指定指示存储区中的数据项的位置的m位立即值的指令。编译装置根据一个数据属性从由多个数据项组成的组X中依次选择数据项; 并且每当选择数据项时，判断所选择的数据项是否可分配给n字节存储区（n <= 2 ^{m）。当判断为否定时，编译装置根据不同的数据属性指定所有选择的数据项中的数据项，并从组X中排除指定的数据项，并重复选择，直到剩余的所有数据项在排除指定数据项之后的组X被判断为可分配给存储区。}

2. 发明申请

US20080141229A1 PROCESSOR, PROGRAM CONVERSION APPARATUS, PROGRAM CONVERSION METHOD, AND COMPUTER PROGRAM 审中-公开
标题翻译：处理器，程序转换装置，程序转换方法和计算机程序
公开(公告)号：US20080141229A1
公开(公告)日：2008-06-12
申请号：US11969083
申请日：2008-01-03
申请人： Taketo Heishi , Hajime Ogawa , Shuichi Takayama , Toshiyuki Sakata , Shohei Michimoto
发明人： Taketo Heishi , Hajime Ogawa , Shuichi Takayama , Toshiyuki Sakata , Shohei Michimoto
IPC分类号： G06F9/45 , G06F9/312
CPC分类号： G06F9/30094 , G06F9/30021 , G06F9/30072
摘要： The first, second, and third operating units 441 to 443 each perform a predetermined operation according to an instruction before a point of time partway through a clock cycle. When having performed a comparison operation, each operating unit outputs a result value to the condition flag operating unit 51. The condition flag operating unit 51 calculates a new condition flag value by performing a logical operation on either (a) a value that has been read from the condition flag register 46 and the result value or (b) the result values themselves. The condition flag operating unit 51 outputs, before the clock cycle ends, the new condition flag value to one of the first, second, and third gates 451 to 453 that is related to a conditional instruction so as to control nullification of the conditional new condition flag value.
摘要翻译：第一，第二和第三操作单元441至443各自根据在时钟周期的中途的时间点之前的指令执行预定的操作。当执行比较操作时，每个操作单元将结果值输出到条件标志操作单元51。条件标志操作单元51通过对（a）从条件标志寄存器46读取的值和结果值或（b）结果值本身执行逻辑运算来计算新条件标志值。条件标志操作单元51在时钟周期结束之前将新条件标志值输出到与条件指令相关的第一，第二和第三门451至453中的一个，以便控制条件新条件的无效标志值。

3. 发明授权

US07698696B2 Compiler apparatus with flexible optimization 有权
标题翻译：具有灵活优化的编译器
公开(公告)号：US07698696B2
公开(公告)日：2010-04-13
申请号：US10608040
申请日：2003-06-30
申请人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
发明人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/443
摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.
摘要翻译：编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元，根据来自分析单元等的指令等，执行由用户选择和编译指定的单独优化处理的“if”转换单元和一对指令生成单元）。全局区域分配单元执行优化处理指定要分配给全球区域的变量的最大数据大小，指定要分配给全局区域的变量，以及关于指定未分配给全局区域的变量的选项和编译指示。

4. 发明授权

US07254807B2 Program conversion apparatus, program conversion method, and computer program for executing program conversion process 有权
标题翻译：程序转换装置，程序转换方法和用于执行程序转换处理的计算机程序
公开(公告)号：US07254807B2
公开(公告)日：2007-08-07
申请号：US10315877
申请日：2002-12-10
申请人： Toshiyuki Sakata , Taketo Heishi , Hajime Ogawa , Shohei Michimoto , Shuichi Takayama
发明人： Toshiyuki Sakata , Taketo Heishi , Hajime Ogawa , Shohei Michimoto , Shuichi Takayama
IPC分类号： G06F9/45
CPC分类号： G06F8/41 , G06F9/44521 , G06F9/44542
摘要： A compiling unit (110) generates indefinite branch information showing that an instruction set to be selected is indefinite, instead of generating a branch instruction. A linking unit (130) generates an appropriate direct addressing branch instruction by judging whether an instruction set used at a branch source and an instruction set used at a branch destination are the same. Also, one reference instruction set is determined. The compiling unit (110) adds a mode adjusting instruction that belongs to the reference instruction set and that is for causing a branch to an instruction placed at a branch destination and for selecting the instruction set that is originally to be selected. The mode adjusting instruction provides an alternative branch destination corresponding to an original branch destination, and the compiling unit (110) generates an indirect addressing branch instruction for causing a branch to the alternative branch destination and for selecting the reference instruction set.
摘要翻译：编译单元（110）产生不确定的分支信息，表示选择的指令集是不确定的，而不是生成分支指令。链接单元（130）通过判断在分支源使用的指令集和在分支目的地使用的指令集是否相同来生成适当的直接寻址分支指令。此外，确定一个参考指令集。编译单元（110）添加属于参考指令集的模式调整指令，其用于使分支到位于分支目的地的指令，并且用于选择最初被选择的指令集。模式调整指令提供与原始分支目的地相对应的替代分支目的地，并且编译单元（110）生成用于使分支到备选分支目的地并用于选择参考指令集的间接寻址分支指令。

5. 发明授权

US08418157B2 Compiler apparatus with flexible optimization 有权
标题翻译：具有灵活优化的编译器
公开(公告)号：US08418157B2
公开(公告)日：2013-04-09
申请号：US12706329
申请日：2010-02-16
申请人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
发明人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.
摘要翻译：编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元，如果转换单元和配对指令生成单元）执行来自用户的选项和编译指示的单独优化处理，遵循来自分析单元的指令等。全局区域分配单元执行优化处理，在指定要分配给全局区域的变量的最大数据大小，要分配给全局区域的变量的指定，以及关于在全局区域中未分配的变量的指定的选项和编译指示。

6. 发明申请

US20100175056A1 COMPILER APPARATUS WITH FLEXIBLE OPTIMIZATION 有权
标题翻译：具有灵活优化的编译器
公开(公告)号：US20100175056A1
公开(公告)日：2010-07-08
申请号：US12706329
申请日：2010-02-16
申请人： Hajime OGAWA , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
发明人： Hajime OGAWA , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/443
摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.
摘要翻译：编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元，根据来自分析单元等的指令等，执行由用户选择和编译指定的单独优化处理的“if”转换单元和一对指令生成单元）。全局区域分配单元执行优化处理指定要分配给全球区域的变量的最大数据大小，指定要分配给全局区域的变量，以及关于指定未分配给全局区域的变量的选项和编译指示。

7. 发明授权

US07076638B2 Processor, compiler and compilation method 有权
公开(公告)号：US07076638B2
公开(公告)日：2006-07-11
申请号：US10246482
申请日：2002-09-19
申请人： Taketo Heishi , Shuichi Takayama , Tetsuya Tanaka , Hajime Ogawa , Nobuo Higaki
发明人： Taketo Heishi , Shuichi Takayama , Tetsuya Tanaka , Hajime Ogawa , Nobuo Higaki
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/30072 , G06F9/3822
摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

8. 发明授权

US07073169B2 Compiler device with branch instruction inserting unit 有权
标题翻译：具有分支指令插入单元的编译器
公开(公告)号：US07073169B2
公开(公告)日：2006-07-04
申请号：US10174108
申请日：2002-06-17
申请人： Hajime Ogawa , Shuichi Takayama , Taketo Heishi , Nobuo Higaki
发明人： Hajime Ogawa , Shuichi Takayama , Taketo Heishi , Nobuo Higaki
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： A compiler device includes a conditional-executable-instruction generation unit and a branch instruction insertion unit. The conditional-executable-instruction generation unit generates a conditional executable instruction that is executed when a condition that the conditional executable instruction refers to is satisfied. In the case where there is a section containing a non-executive condition under which no instruction is executed in one cycle or a plurality of cycles in series, the branch instruction insertion unit inserts a conditional branch instruction that refers to the non-executive condition and instructs to branch to a cycle immediately after a last cycle of the section, to after an instruction of a cycle immediately before a start of the section. Thus, a compiler device employing conditional executable instructions is provided that is capable of generating an assembler code that does not degrade the performance when the instructions are executed, even if a source program includes a branch instruction that causes a then part and an else part to be executed through unbalanced numbers of cycles, respectively.
摘要翻译：编译器装置包括条件可执行指令生成单元和分支指令插入单元。条件可执行指令生成单元生成当满足条件可执行指令引用的条件时执行的条件可执行指令。在存在包含在一个周期或多个周期中不执行指令的非执行条件的部分的情况下，分支指令插入单元插入参考非执行条件的条件分支指令，并且指示在该部分的最后一个周期之后立即分支到一个周期，直到在该部分开始之前的一个周期的指令之后。因此，提供了一种使用条件可执行指令的编译器装置，其能够生成当执行指令时不降低性能的汇编代码，即使源程序包括分支指令，该分支指令导致随后的部分和其他部分分别通过不平衡的周期数执行。

9. 发明申请

US20060031661A1 Processor for executing instructions in units that are unrelated to the units in wihcih instructions are read,and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor 有权
标题翻译：读取用于以与wihcih指令中的单元无关的单元执行指令的处理器，以及用于这种处理器的编译器，优化装置，汇编器，链接器，调试器和反汇编器
公开(公告)号：US20060031661A1
公开(公告)日：2006-02-09
申请号：US11245357
申请日：2005-10-07
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/40
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当指令解码器409a-409c解码分支指令时，包括在分支指令中的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

10. 发明授权

US06904135B2 Compound device and telephone station device connected to the same, and power supply system and portable telephone system using compound device 失效
标题翻译：复合设备和电话站设备连接在一起，电源系统和便携式电话系统使用复合设备
公开(公告)号：US06904135B2
公开(公告)日：2005-06-07
申请号：US10172216
申请日：2002-06-14
申请人： Shuichi Takayama , Nobuo Higaki , Hajime Ogawa , Taketo Heishi
发明人： Shuichi Takayama , Nobuo Higaki , Hajime Ogawa , Taketo Heishi
IPC分类号： H04B1/38 , H04B7/26 , H04M1/00 , H04M1/723 , H04M1/725 , H04N5/44 , H04W4/24 , H04W76/02 , H04W88/02 , H04W88/08 , H04W88/14 , H04M11/00 , H04B1/00
CPC分类号： H04B1/005 , H04B1/3805 , H04M1/725 , H04N5/4401 , H04N21/2408 , H04N21/2543 , H04N21/4126 , H04N21/4263 , H04N21/42676 , H04N21/433 , H04N21/43637 , H04N21/44227 , H04N21/443 , H04N21/6112 , H04N21/6162 , H04N21/6168 , H04N21/654 , H04N21/6582 , H04N21/6583
摘要： A compound device has the structural hardware of a digital television, is connected to an antenna and a telephone station, and by reading out and running either a digital television (DTV) program or a base station program with a general processor, it has both the function of a digital television and the function of a portable telephone base station. The owner of the compound device receives discounts in their subscribed telephone fee or their power fee based on records in a communication record portion. Thus, a compound device in which a digital television is given the function of a portable telephone base station is provided, so that a novel infrastructure can be achieved in which insufficiencies in base stations are made up for without requiring equipment investment expenditures and portable device owners are given financial benefits in compensation for allowing the public use of their private possession as a portable telephone base station.
摘要翻译：复合设备具有数字电视的结构硬件，连接到天线和电话台，并且通过读取和运行数字电视（DTV）程序或使用通用处理器的基站程序，它具有数字电视的功能和便携式电话基站的功能。复合设备的所有者根据通信记录部分中的记录，收到其订阅的电话费或其电费的折扣。因此，提供了数字电视机被赋予便携式电话基站的功能的复合装置，从而可以实现基站的不足之处，不需要设备投资支出和便携式设备所有者的新颖的基础设施给予经济利益，允许公共使用私人拥有作为便携式电话基站。

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