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1. 发明授权

US07184296B2 Memory device 失效
标题翻译：内存设备
公开(公告)号：US07184296B2
公开(公告)日：2007-02-27
申请号：US11069940
申请日：2005-03-03
申请人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C11/00
CPC分类号： G11C16/28
摘要： A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.
摘要翻译：存储器件具有用于连接到存储单元的数据线（DATA-BUS），用于参考的参考线（Reference-BUS），预充电电路（101），负载电路（102）和放大器电路（103））。预充电电路连接到数据线和参考线，并配置为对数据线和参考线进行预充电。负载电路连接到数据线和参考线，并配置为向数据线施加第一恒定电流，并将比第一恒定电流小的第二恒定电流施加到参考线。放大电路连接到数据线和参考线，并被配置为放大数据线与参考线之间的差分电压。

2. 发明授权

US07307885B2 Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit 有权
标题翻译：配有参考电池和负载平衡电路的多值非易失性半导体存储器件
公开(公告)号：US07307885B2
公开(公告)日：2007-12-11
申请号：US11063999
申请日：2005-02-24
申请人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C7/14 , G11C2207/002
摘要： A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of bit lines including a first bit line conected to a selected one of the plurality of memory cells and a plurality of second bit lines connected to non-selected memory cells, a plurality of reference cells supplying different reference currents respectively, and a read-out circuit, wherein, when reading the memory cell information, the read-out circuit is coupled to the first bit line connected to the selected memory cell and coupled to one of the plurality of reference cells through one of the plurality of second bit lines connected to the non-selected memory cells.
摘要翻译：非易失性半导体存储器件包括保持存储单元信息的多个存储器单元，连接到多个存储器单元的多个位线，多个位线包括与多个存储器单元中选择的一个存储单元相连的第一位线以及连接到未选择的存储器单元的多个第二位线，分别提供不同参考电流的多个参考单元和读出电路，其中当读取存储单元信息时，读出电路耦合到所述第一位线连接到所选择的存储器单元，并且通过连接到所述未选择的存储器单元的所述多个第二位线之一耦合到所述多个参考单元中的一个。

3. 发明申请

US20050185465A1 Memory device 审中-公开
标题翻译：内存设备
公开(公告)号：US20050185465A1
公开(公告)日：2005-08-25
申请号：US11110700
申请日：2005-04-21
申请人： Nobutaka Taniguchi , Atsushi Hatakeyama , Toshimi Ikeda , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Nobutaka Taniguchi , Atsushi Hatakeyama , Toshimi Ikeda , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C8/12 , G11C11/34 , G11C16/26
CPC分类号： G11C16/26 , G11C8/12
摘要： A memory device includes plural banks (BNKA, BNKB, BNKC, and BNKD), and each of the banks includes a plural memory cells storing data and plural bit lines reading data from the plural memory cells. Bit line lengths of all of the plural banks are equal.
摘要翻译：存储器件包括多个存储体（BNKA，BNKB，BNKC和BNKD），并且每个存储体包括存储数据的多个存储单元和从多个存储单元读取数据的多个位线。所有多个组的位线长度相等。

4. 发明申请

US20050141306A1 Memory device 失效
标题翻译：内存设备
公开(公告)号：US20050141306A1
公开(公告)日：2005-06-30
申请号：US11069940
申请日：2005-03-03
申请人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C5/06 , G11C16/06 , G11C16/28
CPC分类号： G11C16/28
摘要： A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.
摘要翻译：存储器件具有用于连接到存储单元的数据线（DATA-BUS），用于参考的参考线（Reference-BUS），预充电电路（101），负载电路（102）和放大器电路（103））。预充电电路连接到数据线和参考线，并配置为对数据线和参考线进行预充电。负载电路连接到数据线和参考线，并配置为向数据线施加第一恒定电流，并将比第一恒定电流小的第二恒定电流施加到参考线。放大电路连接到数据线和参考线，并被配置为放大数据线与参考线之间的差分电压。

5. 发明申请

US20050162955A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050162955A1
公开(公告)日：2005-07-28
申请号：US11063999
申请日：2005-02-24
申请人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C7/14 , G11C16/26 , G11C16/28 , G11C7/02 , G11C8/00
CPC分类号： G11C16/28 , G11C7/14 , G11C2207/002
摘要： A nonvolatile semiconductor memory device comprises a memory cell array in which memory cells each holding memory cell information are arrayed, reference cells which supply different reference currents respectively, and a read-out circuit. When reading the memory cell information from a selected one of the memory cells, the read-out circuit is brought into conduction to a first global bit line which is connected to a bit line of the selected memory cell, and brought into conduction to one of a plurality of second global bit lines respectively which are provided near the first global bit line and connected to bit lines of non-selected memory cells but not connected to the bit line of the selected memory cell, so that the memory cell information is determined by comparing a read-out current from the selected memory cell with each of the reference currents from the reference cells.
摘要翻译：非易失性半导体存储器件包括其中排列存储单元信息的存储器单元的存储单元阵列，分别提供不同参考电流的参考单元和读出电路。当从所选存储单元中读出存储单元信息时，读出电路被导通到连接到所选存储单元的位线的第一全局位线，并导通到多个第二全局位线分别设置在第一全局位线附近并连接到未选择的存储器单元的位线，但未连接到所选存储单元的位线，使得存储器单元信息由将来自所选存储器单元的读出电流与来自参考单元的每个参考电流进行比较。

6. 发明授权

US06288585B1 Semiconductor device using external power voltage for timing sensitive signals 有权
标题翻译：半导体器件使用外部电源电压进行时序敏感信号
公开(公告)号：US06288585B1
公开(公告)日：2001-09-11
申请号：US09535745
申请日：2000-03-27
申请人： Yoshihide Bando , Nobutaka Taniguchi , Hiroyoshi Tomita , Kota Hara , Naoharu Shinozaki
发明人： Yoshihide Bando , Nobutaka Taniguchi , Hiroyoshi Tomita , Kota Hara , Naoharu Shinozaki
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.
摘要翻译：接收稳定的外部电源电压的半导体器件包括产生内部降低的电源电压的降压产生电路，基于内部降低的电源电压进行操作的输入电路，使内部降低的电源电压波动，控制电路，其产生内部时钟信号;输出电路，其响应于内部时钟信号以输出定时将数据信号输出到设备的外部;时钟传送电路，其传送来自时钟控制电路的内部时钟信号到输出电路，并且基于外部电源电压进行操作，以使得输出定时基本上不受内部降低的功率电压的波动的影响。

7. 发明申请

US20060176092A1 Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero 失效
标题翻译：延迟输出信号的相位的延迟时间调整方法，直到输入信号和输出信号之间的相位差成为零以外的周期的整数
公开(公告)号：US20060176092A1
公开(公告)日：2006-08-10
申请号：US11395130
申请日：2006-04-03
申请人： Nobutaka Taniguchi
发明人： Nobutaka Taniguchi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/085
摘要： A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises the step of delaying the phase of the output signal until a phase difference between the phase of the input signal and the phase of the output signal becomes N periods, where N is an integer other than zero.
摘要翻译：延迟时间调整方法调整输入信号的延迟时间，使得输入信号的相位和输出信号的相位彼此匹配。延迟时间调整方法包括延迟输出信号的相位，直到输入信号的相位和输出信号的相位之间的相位差成为N个周期，其中N是除零之外的整数。

8. 发明授权

US06522182B2 Integrated circuit device incorporating DLL circuit 有权
标题翻译：集成电路器件结合DLL电路
公开(公告)号：US06522182B2
公开(公告)日：2003-02-18
申请号：US09385008
申请日：1999-08-27
申请人： Hiroyoshi Tomita , Naoharu Shinozaki , Nobutaka Taniguchi , Waichirou Fujieda , Yasuharu Sato , Kenichi Kawasaki , Masafumi Yamazaki , Kazuhiro Ninomiya
发明人： Hiroyoshi Tomita , Naoharu Shinozaki , Nobutaka Taniguchi , Waichirou Fujieda , Yasuharu Sato , Kenichi Kawasaki , Masafumi Yamazaki , Kazuhiro Ninomiya
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G11C7/1072 , G11C7/222 , H03K5/131
摘要： In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit. Also, by connecting the first external earthing power source to the variable delay circuit and/or phase coincidence detection unit, the effect of power source noise from the second external earthing power source originating from the operation of circuits other than these is suppressed.
摘要翻译：在本发明中，提供给集成电路装置的外部电源被分成用于DLL电路的第一外部电源和除了DLL电路以外的电路的第二外部电源。根据本发明，通过利用第一外部电源优选用于DLL电路的可变延迟电路，而将第二外部电源中产生的电源噪声不能传输到可变延迟电路，甚至更优选地用于其延迟单位。此外，优选地，通过利用DLL电路的相位比较电路中的相位一致检测单元的第一电源，将第二外部电源中产生的电源噪声不能发送到相位一致检测单元。此外，通过将第一外部接地电源连接到可变延迟电路和/或相位一致检测单元，抑制源于除了这些以外的电路的操作的来自第二外部接地电源的电源噪声的影响。

9. 发明授权

US6031788A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US6031788A
公开(公告)日：2000-02-29
申请号：US207335
申请日：1998-12-08
申请人： Yoshihide Bando , Nobutaka Taniguchi , Hiroyoshi Tomita
发明人： Yoshihide Bando , Nobutaka Taniguchi , Hiroyoshi Tomita
IPC分类号： G11C11/407 , G06F1/04 , G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： A semiconductor integrated circuit is adapted to make invalid an external clock, externally supplied to the semiconductor integrated circuit, when the semiconductor integrated circuit is set in an active power-down state. The semiconductor integrated circuit includes a delay locked loop DLL circuit which outputs an internal clock which phase is synchronized to the external clock. A latch circuit retains control signals in synchronism with the internal clock output by the DLL circuit. An internal circuit performs a predetermined process based on the control signals supplied from the latch circuit.
摘要翻译：当半导体集成电路处于有功掉电状态时，半导体集成电路适于使外部提供给半导体集成电路的外部时钟无效。半导体集成电路包括延迟锁定环DLL电路，其输出与外部时钟同步的内部时钟。锁存电路保持与DLL电路的内部时钟输出同步的控制信号。内部电路基于从锁存电路提供的控制信号执行预定处理。

10. 发明授权

US07667509B2 Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero 失效
标题翻译：延迟输出信号的相位的延迟时间调整方法，直到输入信号和输出信号之间的相位差成为零以外的周期的整数
公开(公告)号：US07667509B2
公开(公告)日：2010-02-23
申请号：US11395130
申请日：2006-04-03
申请人： Nobutaka Taniguchi
发明人： Nobutaka Taniguchi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/085
摘要： A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises the step of delaying the phase of the output signal until a phase difference between the phase of the input signal and the phase of the output signal becomes N periods, where N is an integer other than zero.
摘要翻译：延迟时间调整方法调整输入信号的延迟时间，使得输入信号的相位和输出信号的相位彼此匹配。延迟时间调整方法包括延迟输出信号的相位，直到输入信号的相位和输出信号的相位之间的相位差成为N个周期，其中N是除零之外的整数。

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