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1. 发明申请

US20090122038A1 SEMICONDUCTOR CIRCUIT 审中-公开
标题翻译：半导体电路
公开(公告)号：US20090122038A1
公开(公告)日：2009-05-14
申请号：US12349760
申请日：2009-01-07
申请人： Toshikazu TACHIBANA , Yoshitaka Iwasaki , Kazuya Endo , Goro Sakamaki
发明人： Toshikazu TACHIBANA , Yoshitaka Iwasaki , Kazuya Endo , Goro Sakamaki
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/3677
摘要： A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.
摘要翻译：提供了通过集成半导体电路并实现芯片尺寸减小而获得的缩小电路规模的半导体电路和半导体集成电路芯片。为此，使用双解码方法。该方法使用：预解码电路，包括前级的第一解码器，其对八位地址信号的任意位进行解码，以及解码剩余位的前一级的第二解码器; 电平转换电路，其使预解码电路的输出移位; 以及后解码电路，其解码通过电平转换电路进行电平转换的预解码电路中的解码器的解码输出。

2. 发明授权

US07492341B2 Semiconductor circuit 有权
标题翻译：半导体电路
公开(公告)号：US07492341B2
公开(公告)日：2009-02-17
申请号：US10895884
申请日：2004-07-22
申请人： Toshikazu Tachibana , Yoshitaka Iwasaki , Kazuya Endo , Goro Sakamaki
发明人： Toshikazu Tachibana , Yoshitaka Iwasaki , Kazuya Endo , Goro Sakamaki
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G3/3677
摘要： A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.
摘要翻译：提供了通过集成半导体电路并实现芯片尺寸减小而获得的缩小电路规模的半导体电路和半导体集成电路芯片。为此，使用双解码方法。该方法使用：预解码电路，包括前级的第一解码器，其对八位地址信号的任意位进行解码，以及解码剩余位的前一级的第二解码器; 电平转换电路，其使预解码电路的输出移位; 以及后解码电路，其解码通过电平转换电路进行电平转换的预解码电路中的解码器的解码输出。

3. 发明申请

US20060208996A1 Semiconductor circuit 审中-公开
标题翻译：半导体电路
公开(公告)号：US20060208996A1
公开(公告)日：2006-09-21
申请号：US11337583
申请日：2006-01-24
申请人： Toshikazu Tachibana , Yoshitaka Iwasaki , Kazuya Endo , Goro Sakamaki
发明人： Toshikazu Tachibana , Yoshitaka Iwasaki , Kazuya Endo , Goro Sakamaki
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/20 , G09G3/3208 , G09G2310/0267
摘要： A two-stage decode system is provided which uses a pre-stage decoder comprising a pre-stage first decoder which decodes a bit of arbitrary part of address signals and a pre-stage second decoder which decodes the remaining bits, level shifters which respectively shift the levels of outputs of the pre-stage decoder, and post-stage decoders which respectively decode the decode outputs of the respective decoders in the pre-stage decoder, which have been level-shifted by the level shifters.
摘要翻译：提供了一种两级解码系统，其使用包括前级第一解码器的前级解码器，该前级解码器对地址信号的任意部分的位进行解码，以及解码其余位的前级第二解码器，分别移位的电平移位器前级解码器和后级解码器的输出电平分别解码前级解码器中的各个解码器的解码输出，这些译码器已由电平移位器电平移位。

4. 发明申请

US20050057549A1 Semiconductor circuit 有权
标题翻译：半导体电路
公开(公告)号：US20050057549A1
公开(公告)日：2005-03-17
申请号：US10895884
申请日：2004-07-22
申请人： Toshikazu Tachibana , Yoshitaka Iwasaki , Kazuya Endo , Goro Sakamaki
发明人： Toshikazu Tachibana , Yoshitaka Iwasaki , Kazuya Endo , Goro Sakamaki
IPC分类号： G09G3/36 , G02F1/133 , G09F9/00 , G09G3/20 , G09G5/00 , H04N5/66 , H04N5/70
CPC分类号： G09G3/3688 , G09G3/3677
摘要： A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.
摘要翻译：提供了通过集成半导体电路并实现芯片尺寸减小而获得的缩小电路规模的半导体电路和半导体集成电路芯片。为此，使用双解码方法。该方法使用：预解码电路，包括前级的第一解码器，其对八位地址信号的任意位进行解码，以及解码剩余位的前一级的第二解码器; 电平转换电路，其使预解码电路的输出移位; 以及后解码电路，其解码通过电平转换电路进行电平转换的预解码电路中的解码器的解码输出。

5. 发明申请

US20080042951A1 Liquid crystal drive device 审中-公开
标题翻译：液晶驱动装置
公开(公告)号：US20080042951A1
公开(公告)日：2008-02-21
申请号：US11892385
申请日：2007-08-22
申请人： Yasushi Kawasa , Takesada Akiba , Kazuya Endo , Goro Sakamaki
发明人： Yasushi Kawasa , Takesada Akiba , Kazuya Endo , Goro Sakamaki
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3696 , G09G2330/021
摘要： By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp(VCI-VCOML)/Δt, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp(VCOMH−VCI)/Δt. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2. Meanwhile, a discharging current at a time of discharging from the first voltage VCOMH to the second voltage VCOML is the sum of a discharging current from the first voltage VCOMH to the ground potential GND, Idis1=Cp(VCOMH−GND)/Δt, and a discharging current from the ground potential GND to the second voltage VCOML, Idis2=Cp(GND-VCOML)/Δt. Now, if converted in terms of power consumed at the reference voltage VCI, since Idis1 represents discharge to GND, power consumption thereby becomes zero. Then, consumed power due to the discharging current from the ground potential GND to the second voltage VCOML, Idis2, is VCI×Idis2.
摘要翻译：通过将从液晶驱动装置的电源施加的共电极电压的功率分别实现为液晶显示面板的公共电极互连，能够实现液晶显示面板的整体功耗的降低。从第二电压VCOML到第一电压VCOMH的充电过程中的VCOM操作波形示出充电电流Icha表示从VCOML到参考电压VCI的充电电流之和Icha 1 = Cp（VCI-VCOML）/ Deltat ，以及从参考电压VCI到第一电压VCOMH，Icha 2 = Cp（VCOMH-VCI）/ Deltat的充电电流。因此，Icha1消耗的功率是参考电压VCIxIcha1，Icha2消耗的功率是VCIxIcha 2×2。同时，从第一电压VCOMH向第二电压VCOML放电时的放电电流是从第一电压VCOMH到地电位GND的放电电流Idis 1 = Cp（VCOMH-GND）/ Deltat，和从地电位GND到第二电压VCOML的放电电流Idis 2 = Cp（GND-VCOML）/ Deltat。现在，如果以参考电压VCI消耗的功率转换，由于Idis 1表示放电到GND，因此功耗为零。然后，由于从地电位GND到第二电压VCOML，Idis2的放电电流的消耗功率为VCIxIdis 2。

6. 发明授权

US07342562B2 Liquid crystal drive device 有权
标题翻译：液晶驱动装置
公开(公告)号：US07342562B2
公开(公告)日：2008-03-11
申请号：US10830072
申请日：2004-04-23
申请人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
发明人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3696 , G09G2330/021
摘要： By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained.A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp (VCI−VCOML)/Δt, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp (VCOMH−VCI)/Δt. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2. Meanwhile, a discharging current at a time of discharging from the first voltage VCOMH to the second voltage VCOML is the sum of a discharging current from the first voltage VCOMH to the ground potential GND, Idis1=Cp (VCOMH−GND)/Δt, and a discharging current from the ground potential GND to the second voltage VCOML, Idis2=Cp (GND−VCOML)/Δt. Now, if converted in terms of power consumed at the reference voltage VCI, since Idis1 represents discharge to GND, power consumption thereby becomes zero. Then, consumed power due to the discharging current from the ground potential GND to the second voltage VCOML, Idis2, is VCI×Idis2.
摘要翻译：通过将从液晶驱动装置的电源施加的共电极电压的功率分别实现为液晶显示面板的公共电极互连，能够实现液晶显示面板的整体功耗的降低。从第二电压VCOML到第一电压VCOMH的充电过程中的VCOM操作波形示出充电电流Icha表示从VCOML到参考电压VCI的充电电流之和Icha 1 = Cp（VCI-VCOML）/ Deltat ，以及从参考电压VCI到第一电压VCOMH，Icha 2 = Cp（VCOMH-VCI）/ Deltat的充电电流。因此，Icha1消耗的功率是参考电压VCIxIcha1，Icha2消耗的功率是VCIxIcha 2×2。同时，从第一电压VCOMH向第二电压VCOML放电时的放电电流是从第一电压VCOMH到地电位GND的放电电流Idis 1 = Cp（VCOMH-GND）/ Deltat，和从地电位GND到第二电压VCOML的放电电流Idis 2 = Cp（GND-VCOML）/ Deltat。现在，如果以参考电压VCI消耗的功率转换，由于Idis 1表示放电到GND，因此功耗为零。然后，由于从地电位GND到第二电压VCOML，Idis2的放电电流的消耗功率为VCIxIdis 2。

7. 发明申请

US20070296665A1 Liquid crystal drive device 审中-公开
标题翻译：液晶驱动装置
公开(公告)号：US20070296665A1
公开(公告)日：2007-12-27
申请号：US11892619
申请日：2007-08-24
申请人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
发明人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3696 , G09G2330/021
摘要： By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp (VCI−VCOML)/Δt, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp (VCOMH−VCI)/Δt. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2. Meanwhile, a discharging current at a time of discharging from the first voltage VCOMH to the second voltage VCOML is the sum of a discharging current from the first voltage VCOMH to the ground potential GND, Idis1=Cp (VCOMH−GND)/Δt, and a discharging current from the ground potential GND to the second voltage VCOML, Idis2=Cp (GND−VCOML)/Δt. Now, if converted in terms of power consumed at the reference voltage VCI, since Idis1 represents discharge to GND, power consumption thereby becomes zero. Then, consumed power due to the discharging current from the ground potential GND to the second voltage VCOML, Idis2, is VCI×Idis2.
摘要翻译：通过将从液晶驱动装置的电源施加的共电极电压的功率分别实现为液晶显示面板的公共电极互连，能够实现液晶显示面板的整体功耗的降低。从第二电压VCOML到第一电压VCOMH的充电过程中的VCOM操作波形示出充电电流Icha表示从VCOML到参考电压VCI的充电电流之和Icha 1 = Cp（VCI-VCOML）/ Deltat ，以及从参考电压VCI到第一电压VCOMH，Icha 2 = Cp（VCOMH-VCI）/ Deltat的充电电流。因此，Icha1消耗的功率是参考电压VCIxIcha1，Icha2消耗的功率是VCIxIcha 2×2。同时，从第一电压VCOMH向第二电压VCOML放电时的放电电流是从第一电压VCOMH到地电位GND的放电电流Idis 1 = Cp（VCOMH-GND）/ Deltat，和从地电位GND到第二电压VCOML的放电电流Idis 2 = Cp（GND-VCOML）/ Deltat。现在，如果以参考电压VCI消耗的功率转换，由于Idis 1表示放电到GND，因此功耗为零。然后，由于从地电位GND到第二电压VCOML，Idis2的放电电流的消耗功率为VCIxIdis 2。

8. 发明申请

US20080049480A1 Semiconductor integrated circuit with voltage generation circuit, liquid crystal display controller and mobile electric equipment 有权
公开(公告)号：US20080049480A1
公开(公告)日：2008-02-28
申请号：US11907536
申请日：2007-10-15
申请人： Kazuya Endo , Naoki Miyamoto , Toshio Mizuno , Takayuki Nakaji , Takatoshi Uchida , Kazuo Ookado , Yoshikazu Yokota
发明人： Kazuya Endo , Naoki Miyamoto , Toshio Mizuno , Takayuki Nakaji , Takatoshi Uchida , Kazuo Ookado , Yoshikazu Yokota
IPC分类号： H02M1/00 , G09G3/36 , H03K3/01
CPC分类号： G09G3/3622 , G09G3/3611 , G09G3/3696 , G09G2310/0245 , G09G2310/0278 , G09G2310/08 , G09G2330/02 , G09G2330/021 , G09G2330/026 , H02M3/07 , H02M2003/071
摘要： There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.

9. 发明申请

US20050192790A1 Serial communication system and serial communication local terminal 审中-公开
标题翻译：串行通信系统和串行通信本地终端
公开(公告)号：US20050192790A1
公开(公告)日：2005-09-01
申请号：US10837035
申请日：2004-04-30
申请人： Kazuya Endo , Tohru Nonaka
发明人： Kazuya Endo , Tohru Nonaka
IPC分类号： G06F13/38 , G05B19/042 , G06F9/455
CPC分类号： G06F13/385 , G05B19/042 , G05B2219/25133 , G05B2219/25182
摘要： The invention is provided to make interface logic unnecessary and simplify a control system in a serial communication system for putting a line connecting a CPU and a control IC into serial form. The serial communication system 1 of the present invention comprises a center terminal 10, connected to the CPU 50 via the CPU control bus, for converting at least the operation instructions from a parallel signal to a serial signal for transmission to the serial communication line 30, and a local terminal 20, connected to the center terminal 10 via the serial communication line 30, for reconverting at least the serially converted operation instructions back to a parallel signal for transmission to the control IC 60. The local terminal 20 comprises a CPU emulation controller 2 for providing the CPU control bus in a pseudo manner, and is connected to the control IC 60 via the pseudo CPU control bus provided by the CPU emulation controller 21.
摘要翻译：提供本发明以使接口逻辑不必要并简化串行通信系统中的控制系统，用于将连接CPU和控制IC的线路串行连接。本发明的串行通信系统1包括：中央终端10，经由CPU控制总线连接到CPU 50，用于至少将来自并行信号的操作指令转换为串行信号以传输到串行通信线路30，以及经由串行通信线路30连接到中心终端10的本地终端20，用于将至少串行转换的操作指令重新转换回并行信号以传输到控制IC 60.本地终端20包括CPU仿真控制器 2，用于以伪方式提供CPU控制总线，并且经由CPU仿真控制器21提供的伪CPU控制总线连接到控制IC 60。

10. 发明授权

US07480164B2 Semiconductor integrated circuit with voltage generation circuit, liquid crystal display controller and mobile electric equipment 有权
公开(公告)号：US07480164B2
公开(公告)日：2009-01-20
申请号：US11907536
申请日：2007-10-15
申请人： Kazuya Endo , Naoki Miyamoto , Toshio Mizuno , Takayuki Nakaji , Takatoshi Uchida , Kazuo Ookado , Yoshikazu Yokota
发明人： Kazuya Endo , Naoki Miyamoto , Toshio Mizuno , Takayuki Nakaji , Takatoshi Uchida , Kazuo Ookado , Yoshikazu Yokota
IPC分类号： H02M1/00 , H03K3/01 , G09G3/36 , G05F1/40
CPC分类号： G09G3/3622 , G09G3/3611 , G09G3/3696 , G09G2310/0245 , G09G2310/0278 , G09G2310/08 , G09G2330/02 , G09G2330/021 , G09G2330/026 , H02M3/07 , H02M2003/071
摘要： There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.

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