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1. 发明授权

US07529126B2 Nonvolatile memory device and semiconductor device 有权
标题翻译：非易失性存储器件和半导体器件
公开(公告)号：US07529126B2
公开(公告)日：2009-05-05
申请号：US11472993
申请日：2006-06-23
申请人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
发明人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0433
摘要： Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1iA to flow a current in the memory cell.
摘要翻译：这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。并且，在恒定电流源晶体管中流动约1iA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

2. 发明授权

US07085157B2 Nonvolatile memory device and semiconductor device 有权
标题翻译：非易失性存储器件和半导体器件
公开(公告)号：US07085157B2
公开(公告)日：2006-08-01
申请号：US10805365
申请日：2004-03-22
申请人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
发明人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0433
摘要： A method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 ìA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 ìA to flow a current in the memory cell.
摘要翻译：一种用于通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入和降低功耗的方法。当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。并且，在恒定电流源晶体管中流动约1AA的恒定电流，并且通过约1μA的恒定电流放电位线以使存储器单元中的电流流动。

3. 发明申请

US20060239072A1 Nonvolatile memory device and semiconductor device 有权
标题翻译：非易失性存储器件和半导体器件
公开(公告)号：US20060239072A1
公开(公告)日：2006-10-26
申请号：US11472993
申请日：2006-06-23
申请人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
发明人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/10 , G11C16/0433
摘要： Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.
摘要翻译：这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。并且，在恒定电流源晶体管中流动约1IA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

4. 发明授权

US08017986B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08017986B2
公开(公告)日：2011-09-13
申请号：US12718111
申请日：2010-03-05
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

5. 发明授权

US07414283B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07414283B2
公开(公告)日：2008-08-19
申请号：US11415129
申请日：2006-05-02
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

6. 发明申请

US20060044871A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20060044871A1
公开(公告)日：2006-03-02
申请号：US11195684
申请日：2005-08-03
申请人： Hiroyuki Tanikawa , Toshihiro Tanaka , Yutaka Shinagawa , Takashi Yamaki
发明人： Hiroyuki Tanikawa , Toshihiro Tanaka , Yutaka Shinagawa , Takashi Yamaki
IPC分类号： G11C16/06
CPC分类号： G11C16/344
摘要： The present invention is directed to realize both higher reading speed and assurance of the larger number of rewriting times for a nonvolatile memory. A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area for storing information in accordance with a threshold voltage which varies. One or plural conditions out of erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area is/are made different from that/those in the second nonvolatile memory area, speed of reading information stored in the first nonvolatile memory area is higher than that of reading information stored in the second nonvolatile memory area, and the assured number of rewriting times in the second nonvolatile memory area is larger than that in the first nonvolatile memory area.
摘要翻译：本发明旨在实现更高的读取速度和对非易失性存储器的更大数量的重写时间的保证。半导体集成电路具有第一非易失性存储区域和用于根据变化的阈值电压存储信息的第二非易失性存储区域。擦除验证存储器栅极电压，擦除验证确定存储器电流，写入验证确定存储器栅极电压，写入验证确定存储器电流，擦除电压，擦除电压施加时间，写入电压和写入电压施加时间中的一个或多个条件第一非易失性存储器区域与第二非易失性存储区域中的那些不同，第一非易失性存储区域中存储的读取信息的速度高于存储在第二非易失性存储区域中的读取信息的速度，并且确定的数量在第二非易失性存储器区域中的重写次数大于第一非易失性存储器区域中的重写时间。

7. 发明授权

US06963507B2 Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory 有权
公开(公告)号：US06963507B2
公开(公告)日：2005-11-08
申请号：US10419228
申请日：2003-04-21
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
IPC分类号： G11C16/02 , G11C8/02 , G11C16/12 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/12 , G11C2216/14
摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

8. 发明授权

US07286410B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07286410B2
公开(公告)日：2007-10-23
申请号：US11195684
申请日：2005-08-03
申请人： Hiroyuki Tanikawa , Toshihiro Tanaka , Yutaka Shinagawa , Takashi Yamaki
发明人： Hiroyuki Tanikawa , Toshihiro Tanaka , Yutaka Shinagawa , Takashi Yamaki
IPC分类号： G11C16/06
CPC分类号： G11C16/344
摘要： A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area to store information in accordance with a variable threshold voltage. At least one condition of the following conditions of the first nonvolatile memory area is made different from that of the second nonvolatile memory area: erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area.
摘要翻译：半导体集成电路具有第一非易失性存储区域和第二非易失性存储区域，用于根据可变阈值电压存储信息。使第一非易失性存储区域的以下条件的至少一个条件与第二非易失性存储器区域的不同：擦除验证确定存储器栅极电压，擦除验证确定存储器电流，写入验证确定存储器栅极电压，写入验证确定存储器第一非易失性存储器区域中的电流，擦除电压，擦除电压施加时间，写入电压和写入电压施加时间。

9. 发明申请

US20060220100A1 Semicondudctor device 有权
标题翻译：半导体器件
公开(公告)号：US20060220100A1
公开(公告)日：2006-10-05
申请号：US11415129
申请日：2006-05-02
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

10. 发明申请

US20050258474A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050258474A1
公开(公告)日：2005-11-24
申请号：US10484578
申请日：2002-07-22
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

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