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1. 发明授权

US08537603B2 SRAM cell 有权
标题翻译： SRAM单元
公开(公告)号：US08537603B2
公开(公告)日：2013-09-17
申请号：US13384648
申请日：2010-07-02
申请人： Toshihiro Sekigawa , Yohei Matsumoto , Hanpei Koike
发明人： Toshihiro Sekigawa , Yohei Matsumoto , Hanpei Koike
IPC分类号： G11C11/41 , G11C11/412
CPC分类号： H01L27/1104 , G11C11/4125
摘要： The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.
摘要翻译：本发明提供一种SRAM单元，其不具有对晶体管尺寸的限制，以实现稳定的写入和读取操作，每个端口具有较少数量的控制信号线，并且其可以容易地多端口读取操作以及写入操作，使得可以通过单个位线执行写入和读取操作。 SRAM单元包括反馈控制晶体管，用于控制特定的两个反相器之间的正反馈电路的连接或断开，连接到单个位线的写入控制晶体管和读取控制晶体管以及连接到读取控制晶体管的读取缓冲晶体管。

2. 发明申请

US20120120717A1 SRAM CELL 有权
公开(公告)号：US20120120717A1
公开(公告)日：2012-05-17
申请号：US13384648
申请日：2010-07-02
申请人： Toshihiro Sekigawa , Yohei Matsumoto , Hanpei Koike
发明人： Toshihiro Sekigawa , Yohei Matsumoto , Hanpei Koike
IPC分类号： G11C11/412 , G11C11/419
CPC分类号： H01L27/1104 , G11C11/4125
摘要： The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.
摘要翻译：本发明提供一种SRAM单元，其不具有对晶体管尺寸的限制，以实现稳定的写入和读取操作，每个端口具有较少数量的控制信号线，并且其可以容易地多端口读取操作以及写入操作，使得可以通过单个位线执行写入和读取操作。 SRAM单元包括反馈控制晶体管，用于控制特定的两个反相器之间的正反馈电路的连接或断开，连接到单个位线的写入控制晶体管和读取控制晶体管以及连接到读取控制晶体管的读取缓冲晶体管。

3. 发明申请

US20050224884A1 Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same 有权
标题翻译：双栅极MOS晶体管，双栅极CMOS晶体管及其制造方法
公开(公告)号：US20050224884A1
公开(公告)日：2005-10-13
申请号：US11098467
申请日：2005-04-05
申请人： Toshihiro Sekigawa , Yongxun Liu , Meishoku Masahara , Hanpei Koike , Eiichi Suzuki
发明人： Toshihiro Sekigawa , Yongxun Liu , Meishoku Masahara , Hanpei Koike , Eiichi Suzuki
IPC分类号： H01L27/08 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/76 , H01L29/786
CPC分类号： H01L29/785 , H01L27/1211 , H01L29/41733 , H01L29/458 , H01L29/4908 , H01L29/66795
摘要： In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined length and height and a predetermined shape of horizontal section, the semiconductor crystal layer including P-type or N-type source region, channel region, and drain region, in that order, formed therein, a source electrode, gate electrodes, and a drain electrode are provided in contact with side surfaces of the respective regions, and the gate electrodes are provided in contact with the side surfaces of the channel region.
摘要翻译：在双栅MOS晶体管中，依次形成或层叠衬底，绝缘层和半导体层，在半导体层中形成延伸到绝缘层的开口，同时留下岛状区域，岛形状区域，包括具有预定长度和高度以及预定形状的水平截面的半导体晶体层，所述半导体晶体层依次形成有P型或N型源极区，沟道区和漏极区。设置与各个区域的侧表面接触的源电极，栅电极和漏电极，并且栅电极设置成与沟道区的侧表面接触。

4. 发明授权

US06989706B2 Method for application of gating signal in insulated double gate FET 失效
标题翻译：绝缘双栅FET中门控信号的应用方法
公开(公告)号：US06989706B2
公开(公告)日：2006-01-24
申请号：US10808432
申请日：2004-03-25
申请人： Toshihiro Sekigawa , Hanpei Koike , Tadashi Nakagawa
发明人： Toshihiro Sekigawa , Hanpei Koike , Tadashi Nakagawa
IPC分类号： H03K17/687
CPC分类号： H03K3/356017 , H03K3/356069 , H03K17/302 , H03K2217/0018
摘要： In an insulated double gate FET, the threshold voltage during the operation of a transient response thereof is enabled to be arbitrarily and accurately controlled by a method that includes applying a first input signal intended to perform an ordinary logic operation to one of the gate electrodes thereof and applying, in response to this signal, a second signal that has a signal-level temporal-change direction as the first input signal and has at least one of the low level and the high level thereof shifted by a predetermined magnitude or endowed with a predetermined time difference or has the time slower or faster signal level change of the signal to the other gate electrode.
摘要翻译：在绝缘双栅极FET中，其瞬态响应的操作期间的阈值电压能够通过包括将用于执行普通逻辑运算的第一输入信号施加到其栅电极之一的方法来任意和精确地控制以及响应于该信号，将具有作为第一输入信号的信号电平时间变化方向的第二信号和低电平和高电平中的至少一个偏移了预定的量值或赋予了预定的时间差或者将信号的信号电平变化较慢或更快的时间转移到另一个栅电极。

5. 发明申请

US20050097496A1 High-speed and low-power logical unit 审中-公开
标题翻译：高速和低功率逻辑单元
公开(公告)号：US20050097496A1
公开(公告)日：2005-05-05
申请号：US10951759
申请日：2004-09-29
申请人： Hanpei Koike , Tadashi Nakagawa , Toshihiro Sekigawa
发明人： Hanpei Koike , Tadashi Nakagawa , Toshihiro Sekigawa
IPC分类号： H01L27/04 , G06F17/50 , H01L21/82 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/092 , H01L27/118 , H03K19/094 , H03K19/177 , G06F9/45
CPC分类号： G06F17/505 , G06F17/5068 , H01L27/0207
摘要： It is an object of the present invention to provide a high-speed and low-power logical unit formed of a master slice integrated circuit, which offers advantages of reducing the cost and time required for designing masks, and in which a faster operation can be achieved while consuming low power by controlling the operation mode of each logical device forming the logical unit according to the operating state of the corresponding logical device. The high-speed and low-power logical unit comprises a plurality of logical devices including control-voltage input terminals for controlling operation modes, a voltage supply circuit for generating a plurality of different control voltages; and a wiring pattern for supplying a control voltage from the voltage supply circuit for controlling each of the logical devices to operate in an operation mode determined according to an operation of the corresponding transistor to the control-voltage input terminal of the corresponding logical device.
摘要翻译：本发明的目的是提供一种由主片集成电路形成的高速和低功率逻辑单元，其提供了降低设计掩模所需的成本和时间的优点，并且其中较快的操作可以是通过根据对应的逻辑设备的操作状态控制形成逻辑单元的每个逻辑设备的操作模式，同时消耗低功率。高速和低功率逻辑单元包括多个逻辑设备，包括用于控制操作模式的控制电压输入端子，用于产生多个不同控制电压的电压供应电路; 以及用于从电压供给电路提供控制电压的布线图案，用于控制每个逻辑装置以根据相应晶体管的操作确定的操作模式操作到相应的逻辑装置的控制电压输入端。

6. 发明授权

US07423324B2 Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same 有权
标题翻译：双栅极MOS晶体管，双栅极CMOS晶体管及其制造方法
公开(公告)号：US07423324B2
公开(公告)日：2008-09-09
申请号：US11098467
申请日：2005-04-05
申请人： Toshihiro Sekigawa , Yongxun Liu , Meishoku Masahara , Hanpei Koike , Eiichi Suzuki
发明人： Toshihiro Sekigawa , Yongxun Liu , Meishoku Masahara , Hanpei Koike , Eiichi Suzuki
IPC分类号： H01L27/01 , H01L27/12 , H01L29/00 , H01L27/10 , H01L29/739 , H01L29/73 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L31/062
CPC分类号： H01L29/785 , H01L27/1211 , H01L29/41733 , H01L29/458 , H01L29/4908 , H01L29/66795
摘要： In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined length and height and a predetermined shape of horizontal section, the semiconductor crystal layer including P-type or N-type source region, channel region, and drain region, in that order, formed therein, a source electrode, gate electrodes, and a drain electrode are provided in contact with side surfaces of the respective regions, and the gate electrodes are provided in contact with the side surfaces of the channel region.
摘要翻译：在双栅MOS晶体管中，依次形成或层叠衬底，绝缘层和半导体层，在半导体层中形成延伸到绝缘层的开口，同时留下岛状区域，岛形状区域，包括具有预定长度和高度以及预定形状的水平截面的半导体晶体层，所述半导体晶体层依次形成有P型或N型源极区，沟道区和漏极区。设置与各个区域的侧表面接触的源电极，栅电极和漏电极，并且栅电极设置成与沟道区的侧表面接触。

7. 发明授权

US07282959B2 CMOS circuit including double-insulated-gate field-effect transistors 失效
标题翻译： CMOS电路包括双绝缘栅场效应晶体管
公开(公告)号：US07282959B2
公开(公告)日：2007-10-16
申请号：US11072401
申请日：2005-03-07
申请人： Toshihiro Sekigawa , Hanpei Koike , Yongxun Liu , Meishoku Masahara
发明人： Toshihiro Sekigawa , Hanpei Koike , Yongxun Liu , Meishoku Masahara
IPC分类号： H03K19/094
CPC分类号： H01L27/1203 , G11C11/412 , H01L27/1108
摘要： It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.
摘要翻译：本发明的目的是提供使用四端双重绝缘栅场效应晶体管实现的CMOS电路，其中可以克服上述问题。本发明的另一个目的是降低处于空闲状态或就绪状态的电路单元中的功耗，即减少静态功耗。 P型四端子双绝缘栅场效应晶体管的两个栅电极彼此电连接并且电连接到N型四端双绝缘栅的一个栅电极场效应晶体管，由此形成CMOS电路的输入端子，并且通过控制N型四端子双绝缘栅极场效应晶体管的另一个栅极的电位来控制N型四端双重绝缘栅极场效应晶体管的阈值电压型四端双绝缘栅场效应晶体管。

8. 发明申请

US20050199964A1 CMOS circuit including double-insulated-gate field-effect transistors 失效
标题翻译： CMOS电路包括双绝缘栅场效应晶体管
公开(公告)号：US20050199964A1
公开(公告)日：2005-09-15
申请号：US11072401
申请日：2005-03-07
申请人： Toshihiro Sekigawa , Hanpei Koike , Yongxun Liu , Meishoku Masahara
发明人： Toshihiro Sekigawa , Hanpei Koike , Yongxun Liu , Meishoku Masahara
IPC分类号： G11C11/41 , G11C11/412 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/76 , H03K19/0948
CPC分类号： H01L27/1203 , G11C11/412 , H01L27/1108
摘要： It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.
摘要翻译：本发明的目的是提供使用四端双重绝缘栅场效应晶体管实现的CMOS电路，其中可以克服上述问题。本发明的另一个目的是降低处于空闲状态或就绪状态的电路单元中的功耗，即减少静态功耗。 P型四端子双绝缘栅场效应晶体管的两个栅电极彼此电连接并且电连接到N型四端双绝缘栅的一个栅电极场效应晶体管，由此形成CMOS电路的输入端子，并且通过控制N型四端子双绝缘栅极场效应晶体管的另一个栅极的电位来控制N型四端双重绝缘栅极场效应晶体管的阈值电压型四端双绝缘栅场效应晶体管。

9. 发明授权

US07382020B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07382020B2
公开(公告)日：2008-06-03
申请号：US11067699
申请日：2005-03-01
申请人： Yongxun Liu , Toshihiro Sekigawa , Meishoku Masahara , Kenichi Ishii , Eiichi Suzuki
发明人： Yongxun Liu , Toshihiro Sekigawa , Meishoku Masahara , Kenichi Ishii , Eiichi Suzuki
IPC分类号： H01L23/62
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/42384 , H01L29/66795 , H01L2924/0002 , H01L2924/00
摘要： Upstanding thin-film channel regions 5 having different heights are formed between source regions 7 and drain regions 8 of MOS transistors, respectively.
摘要翻译：分别在MOS晶体管的源极区域7和漏极区域8之间形成具有不同高度的直立薄膜沟道区域5。

10. 发明授权

US06630388B2 Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same 失效
公开(公告)号：US06630388B2
公开(公告)日：2003-10-07
申请号：US10095936
申请日：2002-03-13
申请人： Toshihiro Sekigawa , Kenichi Ishii , Eiichi Suzuki
发明人： Toshihiro Sekigawa , Kenichi Ishii , Eiichi Suzuki
IPC分类号： H01L21331
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66545 , H01L29/66795 , H01L29/66818
摘要： A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other. The gate electrodes are formed opposite each other on the same principal surface as the channel region, with the channel region between the electrodes. The source, drain and channel regions are isolated from the surrounding part by a trench, forming an island. Gate insulation films are formed on the opposing side faces of the channel region exposed in the trench. The island region between the gate electrodes is given a width that is less than the length of the channel region to enhance the short channel effect suppressive property of structure.

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