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1. 发明授权

US08537603B2 SRAM cell 有权
标题翻译： SRAM单元
公开(公告)号：US08537603B2
公开(公告)日：2013-09-17
申请号：US13384648
申请日：2010-07-02
申请人： Toshihiro Sekigawa , Yohei Matsumoto , Hanpei Koike
发明人： Toshihiro Sekigawa , Yohei Matsumoto , Hanpei Koike
IPC分类号： G11C11/41 , G11C11/412
CPC分类号： H01L27/1104 , G11C11/4125
摘要： The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.
摘要翻译：本发明提供一种SRAM单元，其不具有对晶体管尺寸的限制，以实现稳定的写入和读取操作，每个端口具有较少数量的控制信号线，并且其可以容易地多端口读取操作以及写入操作，使得可以通过单个位线执行写入和读取操作。 SRAM单元包括反馈控制晶体管，用于控制特定的两个反相器之间的正反馈电路的连接或断开，连接到单个位线的写入控制晶体管和读取控制晶体管以及连接到读取控制晶体管的读取缓冲晶体管。

2. 发明申请

US20120120717A1 SRAM CELL 有权
公开(公告)号：US20120120717A1
公开(公告)日：2012-05-17
申请号：US13384648
申请日：2010-07-02
申请人： Toshihiro Sekigawa , Yohei Matsumoto , Hanpei Koike
发明人： Toshihiro Sekigawa , Yohei Matsumoto , Hanpei Koike
IPC分类号： G11C11/412 , G11C11/419
CPC分类号： H01L27/1104 , G11C11/4125
摘要： The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.
摘要翻译：本发明提供一种SRAM单元，其不具有对晶体管尺寸的限制，以实现稳定的写入和读取操作，每个端口具有较少数量的控制信号线，并且其可以容易地多端口读取操作以及写入操作，使得可以通过单个位线执行写入和读取操作。 SRAM单元包括反馈控制晶体管，用于控制特定的两个反相器之间的正反馈电路的连接或断开，连接到单个位线的写入控制晶体管和读取控制晶体管以及连接到读取控制晶体管的读取缓冲晶体管。

3. 发明申请

US20080282214A1 RECONFIGURABLE INTEGRATED CIRCUIT 有权
标题翻译：可重构集成电路
公开(公告)号：US20080282214A1
公开(公告)日：2008-11-13
申请号：US12103229
申请日：2008-04-15
申请人： Yohei Matsumoto , Hanpei Koike
发明人： Yohei Matsumoto , Hanpei Koike
IPC分类号： G06F17/50 , H01L25/00
CPC分类号： G06F17/5054 , G06F2217/78 , H01L2924/0002 , H01L2924/00
摘要： The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs.A reconfigurable integrated circuit is provided which includes transistors and comprises a first switch with an input terminal, an output terminal, and a control terminal, a first memory with a memory cell connected to the control terminal of the first switch, a second switch capable of shutting down a power supply line or a ground line of the first memory, and a second memory to control the second switch, wherein a value to open the second switch is written into the second memory when the first switch is not operated, thereby shutting down the power supply line or the ground line of the first memory.
摘要翻译：本发明的目的是通过减少SRAM中的漏电流来实现FPGA等可重构集成电路的功耗降低。提供了一种可重构集成电路，其包括晶体管并且包括具有输入端的第一开关，输出端和控制端，具有连接到第一开关的控制端的存储单元的第一存储器，关闭第一存储器的电源线或地线，以及第二存储器来控制第二开关，其中当第一开关不被操作时，打开第二开关的值被写入第二存储器，从而关闭电源线或第一存储器的接地线。

4. 发明授权

US07886250B2 Reconfigurable integrated circuit 有权
标题翻译：可重构集成电路
公开(公告)号：US07886250B2
公开(公告)日：2011-02-08
申请号：US12103229
申请日：2008-04-15
申请人： Yohei Matsumoto , Hanpei Koike
发明人： Yohei Matsumoto , Hanpei Koike
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/78 , H01L2924/0002 , H01L2924/00
摘要： The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs.A reconfigurable integrated circuit is provided which includes transistors and comprises a first switch with an input terminal, an output terminal, and a control terminal, a first memory with a memory cell connected to the control terminal of the first switch, a second switch capable of shutting down a power supply line or a ground line of the first memory, and a second memory to control the second switch, wherein a value to open the second switch is written into the second memory when the first switch is not operated, thereby shutting down the power supply line or the ground line of the first memory.
摘要翻译：本发明的目的是通过减少SRAM中的漏电流来实现FPGA等可重构集成电路的功耗降低。提供了一种可重构集成电路，其包括晶体管并且包括具有输入端的第一开关，输出端和控制端，具有连接到第一开关的控制端的存储单元的第一存储器，关闭第一存储器的电源线或地线，以及第二存储器来控制第二开关，其中当第一开关不被操作时，打开第二开关的值被写入第二存储器，从而关闭电源线或第一存储器的接地线。

5. 发明授权

US07797664B2 System for configuring an integrated circuit and method thereof 有权
标题翻译：用于配置集成电路的系统及其方法
公开(公告)号：US07797664B2
公开(公告)日：2010-09-14
申请号：US11759706
申请日：2007-06-07
申请人： Yohei Matsumoto , Hanpei Koike
发明人： Yohei Matsumoto , Hanpei Koike
IPC分类号： G06F17/50
CPC分类号： H03K19/17748 , G06F17/5054 , H03K19/1778
摘要： With respect to the reconfigurable integrated circuit, a system for configuring an integrated circuit and a configuration method thereof which do not need a circuit overhead for variation correction and diagnosis of variation are provided. A system for configuring an integrated circuit comprises a reconfigurable integrated circuit 101, a memory device for configuring 102 which holds a plurality of different circuit configurations to be realized on the reconfigurable integrated circuit, the circuit configurations having identical functions but having different performance depending on different probability variables, memory device for testing 103 which holds test data to be achieved by the circuit configuration for the respective function, and a test device 104 for performing a test based on the test data.
摘要翻译：关于可重构集成电路，提供了一种用于配置集成电路的系统及其配置方法，其不需要用于变化校正和变化诊断的电路开销。用于配置集成电路的系统包括可重构集成电路101，用于配置102的存储器件，其保存要在可重构集成电路上实现的多个不同电路配置，该电路配置具有相同的功能，但具有不同的性能，具体取决于不同的概率变量，用于测试103的存储器件，其存储要通过相应功能的电路配置实现的测试数据;以及测试设备104，用于基于测试数据执行测试。

6. 发明授权

US07768314B2 Integrated circuit with multidimensional switch topology 失效
标题翻译：具有多维开关拓扑的集成电路
公开(公告)号：US07768314B2
公开(公告)日：2010-08-03
申请号：US11596011
申请日：2005-03-28
申请人： Yohei Matsumoto , Akira Masaki
发明人： Yohei Matsumoto , Akira Masaki
IPC分类号： H03K19/173 , G05F1/10 , H01F38/14
CPC分类号： H03K19/17736 , H01L27/11803 , H03K19/17796
摘要： An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes have poor yield and are difficult to adapt for the production of devices with fine features. In addition, difficulty in heat radiation imposes limits on the number of stacks. The present invention exploits advantages of the 3-dimensional FPGA to deliver FPGAs with high speed/high integration and which resolves difficulty in manufacturing processes. The present invention solves problems by proposing a design method for an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit and a semiconductor integrated circuit including an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit.
摘要翻译： FPGA在其布线架构中需要极大数量的开关，因此显示出低的逻辑密度和低的运行速度。高集成度FPGA的趋势越来越明显。 3维FPGA正在注意其运行速度和逻辑密度的潜在改进。然而，三维一体化处理成品率低，难以适应具有精细特征的装置的生产。此外，热辐射的困难对堆叠数量施加了限制。本发明利用3维FPGA的优点来提供高速/高集成度的FPGA，并且解决了制造过程中的难度。本发明通过提出一种用于FPGA的设计方法来解决问题，其中高维FPGA开关拓扑嵌入在低维集成电路中，以及包括FPGA的半导体集成电路，其中高维FPGA开关拓扑嵌入在较低维数三维集成电路。

7. 发明申请

US20090009215A1 Integrated Circuit with Multidimensional Switch Topology 失效
标题翻译：多维开关拓扑集成电路
公开(公告)号：US20090009215A1
公开(公告)日：2009-01-08
申请号：US11596011
申请日：2005-03-28
申请人： Yohei Matsumoto , Akira Masaki
发明人： Yohei Matsumoto , Akira Masaki
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： H03K19/17736 , H01L27/11803 , H03K19/17796
摘要： An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes have poor yield and are difficult to adapt for the production of devices with fine features. In addition, difficulty in heat radiation imposes limits on the number of stacks. The present invention exploits advantages of the 3-dimensional FPGA to deliver FPGAs with high speed/high integration and which resolves difficulty in manufacturing processes. The present invention solves problems by proposing a design method for an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit and a semiconductor integrated circuit including an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit.
摘要翻译： FPGA在其布线架构中需要极大数量的开关，因此显示出低的逻辑密度和低的运行速度。高集成度FPGA的趋势越来越明显。 3维FPGA正在注意其运行速度和逻辑密度的潜在改进。然而，三维一体化处理成品率低，难以适应具有精细特征的装置的生产。此外，热辐射的困难对堆叠数量施加了限制。本发明利用3维FPGA的优点来提供高速/高集成度的FPGA，并且解决了制造过程中的难度。本发明通过提出一种用于FPGA的设计方法来解决问题，其中高维FPGA开关拓扑嵌入在低维集成电路中，以及包括FPGA的半导体集成电路，其中高维FPGA开关拓扑嵌入在较低维数三维集成电路。

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