会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Two-step parallel analog to digital converter
    • 两级并行模数转换器
    • US4875048A
    • 1989-10-17
    • US237757
    • 1988-08-29
    • Toshihiko ShimizuMasao HottaKenji Maio
    • Toshihiko ShimizuMasao HottaKenji Maio
    • H03M1/14H03M1/00H03M1/10
    • H03M1/10H03M1/16H03M1/361
    • In a two-step parallel analog to digital converter of the type in which a first flash-type A/D converter determines the upper significant bits of a digital signal output having a desired number of bits and after a quantizing error of the first flash-type A/D converter has been determined from the difference between a value obtained by reconverting the upper significant bits to an analog value and the input analog value a second flash-type A/D converter subjects the quantizing error to A/D conversion to determine a digital output of the remaining lower significant bits, a gain correcting circuit is additionally provided to automatically establish a gain of a D/A converter for reconverting the upper significant bits to an analog value on the basis of a reference voltage applied to the first flash-type A/D converter. Moreover, a reference voltage generating circuit is additionally provided to establish upper and lower reference voltages of a second flash-type A/D converter for determining lower significant bits on the basis of the step voltage of the DAC output.
    • 在两级并行模数转换器中,其中第一闪存型A / D转换器确定具有所需位数的数字信号输出的高有效位,并且在第一闪存型A / D转换器的量化误差之后, 已经根据通过将高有效位重新转换为模拟值而获得的值与输入模拟值之间的差确定了A / D转换器,第二闪存型A / D转换器将量化误差对A / D转换进行测量,以确定 附加提供增益校正电路以自动建立D / A转换器的增益,用于根据施加到第一闪存的参考电压将高有效位重新转换为模拟值 型A / D转换器。 此外,另外提供参考电压产生电路以建立第二闪存型A / D转换器的上限和下限参考电压,用于基于DAC输出的阶跃电压来确定较低有效位。
    • 3. 发明授权
    • Encoder
    • 编码器
    • US4851845A
    • 1989-07-25
    • US185264
    • 1988-04-18
    • Masao HottaKenji MaioToshihiko Shimizu
    • Masao HottaKenji MaioToshihiko Shimizu
    • H03M7/00H03M1/00
    • H03M1/361
    • A parallel (flashed) type analog-to-digital converter is provided which is fabricated on a single integrated-circuit chip. An input analog voltage is compared with respective reference voltages by a number of comparators. A change position of an output pattern (for example, a thermometer format signal) of the comparators is detected by a number of exclusive OR circuits. The exclusive OR circuits are grouped into several groups, and in each group, the output transistors of respective exclusive OR circuits are connected to separate bit lines. Several sets of separate bit lines are connected to one set of output bit lines through emitter followers or diodes so that parasitic capacitances related to the output transistors are reduced.
    • 提供了一个并联(闪存)型模数转换器,其被制造在单个集成电路芯片上。 通过多个比较器将输入模拟电压与相应的参考电压进行比较。 比较器的输出图案的变化位置(例如,温度计格式信号)由多个异或电路检测。 异或电路分为几组,每组中各异或电路的输出晶体管连接到分开的位线。 几组单独的位线通过发射极跟随器或二极管连接到一组输出位线,从而减小与输出晶体管相关的寄生电容。
    • 4. 发明授权
    • Analog-to-digital converter
    • 模数转换器
    • US4866444A
    • 1989-09-12
    • US154086
    • 1988-02-09
    • Yoshito NejimeMasao HottaKenji MaioKoichi Ono
    • Yoshito NejimeMasao HottaKenji MaioKoichi Ono
    • H03M1/36H03M1/00H03M1/12
    • H03M1/0809H03M1/365
    • A flash type AD converter includes a group of comparators divided into blocks each including 2.sup.N comparators (N=1, 2, ---), each comparing an input signal with one of a plurality of reference signals, each having individually different voltage levels. One of the comparators may correspond to a level change point where the voltage level of the input signal is higher than that of the reference signal of that comparator which then generates a specific output different from those of the remaining comparators. The converter generates a binary-coded output on the basis of the specific output generated from the level change point comparator. When any one of the plural comparators belonging to one of the blocks generates the specific output, the specific output is applied as an inhibit signal to inhibit appearance of an output from a block including comparators having reference voltage signals with corresponding levels lower than those of the comparators of the block to which the comparator generating the specific output belongs.
    • 闪光型AD转换器包括一组比较器,其被分成块,每个块包括2N个比较器(N = 1,2,...),每个比较器将输入信号与多个参考信号中的一个进行比较,每个参考信号具有单独不同的电压电平。 一个比较器可以对应于电平变化点,其中输入信号的电压电平高于该比较器的参考信号的电平,然后产生与剩余的比较器不同的特定输出。 转换器根据从电平变化点比较器产生的特定输出产生二进制编码输出。 当属于其中一个块的多个比较器中的任何一个产生特定输出时,该特定输出被施加作为禁止信号,以抑制来自包括比较器的输出的出现,该比较器具有的参考电压信号的相应电平低于 生成特定输出的比较器所属的块的比较器。
    • 6. 发明授权
    • Digital-to-analog converter with error compensation
    • 具有误差补偿的数模转换器
    • US4381495A
    • 1983-04-26
    • US195137
    • 1980-10-08
    • Masao HottaKenji MaioNorio YokozawaHiromi Nagaishi
    • Masao HottaKenji MaioNorio YokozawaHiromi Nagaishi
    • H03M1/10H03M1/00H03K13/02
    • H03M1/1071H03M1/74
    • A digital-to-analog conversion system includes a digital-to-analog converter, a source of at least one set of digital input signals and a signal for error compensation and a digital signal for error detection to the converter, a switch to selectively couple either the one set of digital input signals and the signal for error compensation or the signal for error detection to the converter, a clock to generate a switching signal having a predetermined period and duration which is coupled to control the switch, a distribution switch for selectively coupling the output of the digital-to-analog converter to two different terminals, receiving a control input from the clock, a sample and hold circuit to sample and hold the output of the digital-to-analog converter, a detector for detecting a linearity error in the digital-to-analog converter output signal when the digital signal for error detection is coupled as an input thereto, a memory for storing the output of the detector, a circuit to write the output of the detector into the memory, and a circuit to read the data from said memory and couple it as the signal for error compensation at the input to the digital-to-analog converter.
    • 数模转换系统包括数模转换器,至少一组数字输入信号的源和用于误差补偿的信号以及用于向转换器进行错误检测的数字信号,选择性地耦合 一组数字输入信号和用于误差补偿的信号或用于向转换器进行错误检测的信号,产生具有预定周期的切换信号的时钟和耦合以控制开关的持续时间,用于选择性地分配 将数模转换器的输出耦合到两个不同的端子,从时钟接收控制输入,采样和保持电路以采样和保持数模转换器的输出,用于检测线性度的检测器 当用于错误检测的数字信号作为其输入耦合时,数模转换器输出信号中的误差,用于存储检测器的输出的存储器,用于w 将检测器的输出合并到存储器中,以及电路,用于从所述存储器读取数据,并将其作为用于在数模转换器的输入处的误差补偿信号。