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1. 发明授权

US4937579A Method of converting analog signals into digital signals and system for carrying out the method 失效
标题翻译：将模拟信号转换成数字信号的方法和执行该方法的系统
公开(公告)号：US4937579A
公开(公告)日：1990-06-26
申请号：US271652
申请日：1988-11-16
申请人： Kenji Maio , Masao Hotta , Shigeru Watanabe
发明人： Kenji Maio , Masao Hotta , Shigeru Watanabe
IPC分类号： H03M1/12 , G01R13/20 , G06F3/05 , H03M1/18
CPC分类号： H03M1/188
摘要： The same analog signal is inputted to an 8-bit AD converter and to a 4-bit AD converter to obtain an 8-bit digital data and a 4-bit digital data for the same sample value of the analog signal. Values of the 8-bit digital data and 4-bit digital data are compared with each other. The 8-bit digital data is outputted as a digital signal for the sample value of the analog signal when a difference between these values is not greater than one-half the quantity that corresponds to the least significant bit of the 4-bit digital data, and the 4-bit digital data is outputted as a digital signal for the sample value of the analog signal in other cases. There is realized AD conversion which operates apparently at high speeds maintaining high accuracy.
摘要翻译：相同的模拟信号输入到8位AD转换器和4位AD转换器，以获得模拟信号的相同采样值的8位数字数据和4位数字数据。将8位数字数据和4位数字数据的值进行比较。当这些值之间的差不大于与4位数字数据的最低有效位对应的数量的一半时，8位数字数据作为模拟信号采样值的数字信号输出，在其他情况下，4位数字数据作为模拟信号的采样值输出为数字信号。实现了以高速运行的AD转换，保持高精度。

2. 发明授权

US4851845A Encoder 失效
标题翻译：编码器
公开(公告)号：US4851845A
公开(公告)日：1989-07-25
申请号：US185264
申请日：1988-04-18
申请人： Masao Hotta , Kenji Maio , Toshihiko Shimizu
发明人： Masao Hotta , Kenji Maio , Toshihiko Shimizu
IPC分类号： H03M7/00 , H03M1/00
CPC分类号： H03M1/361
摘要： A parallel (flashed) type analog-to-digital converter is provided which is fabricated on a single integrated-circuit chip. An input analog voltage is compared with respective reference voltages by a number of comparators. A change position of an output pattern (for example, a thermometer format signal) of the comparators is detected by a number of exclusive OR circuits. The exclusive OR circuits are grouped into several groups, and in each group, the output transistors of respective exclusive OR circuits are connected to separate bit lines. Several sets of separate bit lines are connected to one set of output bit lines through emitter followers or diodes so that parasitic capacitances related to the output transistors are reduced.
摘要翻译：提供了一个并联（闪存）型模数转换器，其被制造在单个集成电路芯片上。通过多个比较器将输入模拟电压与相应的参考电压进行比较。比较器的输出图案的变化位置（例如，温度计格式信号）由多个异或电路检测。异或电路分为几组，每组中各异或电路的输出晶体管连接到分开的位线。几组单独的位线通过发射极跟随器或二极管连接到一组输出位线，从而减小与输出晶体管相关的寄生电容。

3. 发明授权

US4549166A Digital-to-analog converter using a feedback element matching technique 失效
标题翻译：使用反馈元件匹配技术的数模转换器
公开(公告)号：US4549166A
公开(公告)日：1985-10-22
申请号：US361437
申请日：1982-03-24
申请人： Masao Hotta , Kenji Maio , Hiromi Nagaishi
发明人： Masao Hotta , Kenji Maio , Hiromi Nagaishi
IPC分类号： H03M1/00 , H03K13/05
CPC分类号： H03M1/10 , H03M1/74
摘要： The present invention is characterized that a digital-to-analog converter having ordinal accuracy and one or more current sources are combined and the output currents of the current sources are accurately controlled to have a predetermined relationship with regard to the reference current which is a full-scale value of the analog output current of DAC so that the output current of the current sources designated by bits added to the superior bit of the digital input signal depending on the number of the current sources and the analog output current in response to the digital input signal with the added bits are added to produce an analog signal corresponding to the digital input signal.
摘要翻译：本发明的特征在于，具有顺序精度和一个或多个电流源的数模转换器被组合，并且电流源的输出电流被精确地控制为具有与参考电流相关的预定关系 - DAC的模拟输出电流的规模值，使得根据数字输入信号的上位指定的电流源的输出电流取决于电流源的数量和模拟输出电流响应于数字相加位的输入信号被相加以产生对应于数字输入信号的模拟信号。

4. 发明授权

US4316178A Digital-to-analog conversion system with compensation circuit 失效
标题翻译：具有补偿电路的数模转换系统
公开(公告)号：US4316178A
公开(公告)日：1982-02-16
申请号：US113674
申请日：1980-01-21
申请人： Akinori Shibayama , Kenji Maio , Masao Hotta , Norio Yokozawa
发明人： Akinori Shibayama , Kenji Maio , Masao Hotta , Norio Yokozawa
IPC分类号： H03M1/10 , H03M1/00 , H03K13/02
CPC分类号： H03M1/1071 , H03M1/74
摘要： In a digital-to-analog converter having means to convert a digital input signal into an analog signal, processing means to evaluate an error attendant upon the conversion, and memory means to store the evaluated error; a digital-to-analog converter with a compensating circuit wherein the processing means comprises a ramp voltage generator, a clock pulse generator, and counting means to count clock pulses of the generator and to deliver the error on the basis of the count value of the clock pulses at each time when the ramp voltage exceeds the output of the conversion means.
摘要翻译：在具有将数字输入信号转换为模拟信号的装置的数模转换器中，用于评估转换时伴随的误差的处理装置以及存储评估误差的存储装置; 具有补偿电路的数模转换器，其中所述处理装置包括斜坡电压发生器，时钟脉冲发生器和计数装置，用于对所述发生器的时钟脉冲进行计数，并基于所述发生器的计数值来递送所述误差当斜坡电压超过转换装置的输出时，每个时钟脉冲。

5. 发明授权

US4875048A Two-step parallel analog to digital converter 失效
标题翻译：两级并行模数转换器
公开(公告)号：US4875048A
公开(公告)日：1989-10-17
申请号：US237757
申请日：1988-08-29
申请人： Toshihiko Shimizu , Masao Hotta , Kenji Maio
发明人： Toshihiko Shimizu , Masao Hotta , Kenji Maio
IPC分类号： H03M1/14 , H03M1/00 , H03M1/10
CPC分类号： H03M1/10 , H03M1/16 , H03M1/361
摘要： In a two-step parallel analog to digital converter of the type in which a first flash-type A/D converter determines the upper significant bits of a digital signal output having a desired number of bits and after a quantizing error of the first flash-type A/D converter has been determined from the difference between a value obtained by reconverting the upper significant bits to an analog value and the input analog value a second flash-type A/D converter subjects the quantizing error to A/D conversion to determine a digital output of the remaining lower significant bits, a gain correcting circuit is additionally provided to automatically establish a gain of a D/A converter for reconverting the upper significant bits to an analog value on the basis of a reference voltage applied to the first flash-type A/D converter. Moreover, a reference voltage generating circuit is additionally provided to establish upper and lower reference voltages of a second flash-type A/D converter for determining lower significant bits on the basis of the step voltage of the DAC output.
摘要翻译：在两级并行模数转换器中，其中第一闪存型A / D转换器确定具有所需位数的数字信号输出的高有效位，并且在第一闪存型A / D转换器的量化误差之后，已经根据通过将高有效位重新转换为模拟值而获得的值与输入模拟值之间的差确定了A / D转换器，第二闪存型A / D转换器将量化误差对A / D转换进行测量，以确定附加提供增益校正电路以自动建立D / A转换器的增益，用于根据施加到第一闪存的参考电压将高有效位重新转换为模拟值型A / D转换器。此外，另外提供参考电压产生电路以建立第二闪存型A / D转换器的上限和下限参考电压，用于基于DAC输出的阶跃电压来确定较低有效位。

6. 发明授权

US4866444A Analog-to-digital converter 失效
标题翻译：模数转换器
公开(公告)号：US4866444A
公开(公告)日：1989-09-12
申请号：US154086
申请日：1988-02-09
申请人： Yoshito Nejime , Masao Hotta , Kenji Maio , Koichi Ono
发明人： Yoshito Nejime , Masao Hotta , Kenji Maio , Koichi Ono
IPC分类号： H03M1/36 , H03M1/00 , H03M1/12
CPC分类号： H03M1/0809 , H03M1/365
摘要： A flash type AD converter includes a group of comparators divided into blocks each including 2.sup.N comparators (N=1, 2, ---), each comparing an input signal with one of a plurality of reference signals, each having individually different voltage levels. One of the comparators may correspond to a level change point where the voltage level of the input signal is higher than that of the reference signal of that comparator which then generates a specific output different from those of the remaining comparators. The converter generates a binary-coded output on the basis of the specific output generated from the level change point comparator. When any one of the plural comparators belonging to one of the blocks generates the specific output, the specific output is applied as an inhibit signal to inhibit appearance of an output from a block including comparators having reference voltage signals with corresponding levels lower than those of the comparators of the block to which the comparator generating the specific output belongs.
摘要翻译：闪光型AD转换器包括一组比较器，其被分成块，每个块包括2N个比较器（N = 1,2，...），每个比较器将输入信号与多个参考信号中的一个进行比较，每个参考信号具有单独不同的电压电平。一个比较器可以对应于电平变化点，其中输入信号的电压电平高于该比较器的参考信号的电平，然后产生与剩余的比较器不同的特定输出。转换器根据从电平变化点比较器产生的特定输出产生二进制编码输出。当属于其中一个块的多个比较器中的任何一个产生特定输出时，该特定输出被施加作为禁止信号，以抑制来自包括比较器的输出的出现，该比较器具有的参考电压信号的相应电平低于生成特定输出的比较器所属的块的比较器。

7. 发明授权

US4752767A DA converter 失效
标题翻译： DA转换器
公开(公告)号：US4752767A
公开(公告)日：1988-06-21
申请号：US752588
申请日：1985-07-08
申请人： Kenji Maio , Shinichi Hayashi , Masao Hotta
发明人： Kenji Maio , Shinichi Hayashi , Masao Hotta
IPC分类号： H03M1/68 , H03M1/00 , H03M1/08 , H03M1/66 , H03M1/74
CPC分类号： H03M1/662 , H03M1/0872 , H03M1/687 , H03M1/745 , H03M1/747
摘要： The present invention provides a DA converter of the type wherein a group of switch circuits are controlled in response to input digital signals and a plurality of constant current sources are driven in response to on and off of the switch circuits to convert the input digital signals into analogue signals, the DA converter comprising a plurality of lineages of digital input circuits for controlling the switch circuits, whereby digital signals inputted to the input circuits are changed over in order for each lineage to DA convert them.
摘要翻译：本发明提供了一种类型的DA转换器，其中响应于输入数字信号控制一组开关电路，并且响应于开关电路的导通和关断驱动多个恒流源，以将输入的数字信号转换成模拟信号，DA转换器包括用于控制开关电路的多个数字输入电路谱系，由此输入到输入电路的数字信号被改变，以便每个谱系进行DA转换。

8. 发明授权

US4752766A Analog to digital converter 失效
标题翻译：模数转换器
公开(公告)号：US4752766A
公开(公告)日：1988-06-21
申请号：US15017
申请日：1987-02-17
申请人： Toshihiko Shimizu , Masao Hotta , Kenji Maio
发明人： Toshihiko Shimizu , Masao Hotta , Kenji Maio
IPC分类号： H03M1/36 , H03M1/00 , H03M1/06
CPC分类号： H03M1/361
摘要： In an analog-to-digital converter of a parallel comparison type having a plurality of comparators for comparing an analog input voltage with different reference voltages and converting a comparison result into a digital output by means of an encoder, a plurality of comparators each having a different input dynamic range are used to widen the analog input voltage range up to the power source range of positive and negative voltages.
摘要翻译：在具有用于将模拟输入电压与不同参考电压进行比较的多个比较器并且通过编码器将比较结果转换成数字输出的并行比较类型的模拟 - 数字转换器中，每个具有不同的输入动态范围用于将模拟输入电压范围扩大到正，负电压的电源范围。

9. 发明授权

US4381495A Digital-to-analog converter with error compensation 失效
标题翻译：具有误差补偿的数模转换器
公开(公告)号：US4381495A
公开(公告)日：1983-04-26
申请号：US195137
申请日：1980-10-08
申请人： Masao Hotta , Kenji Maio , Norio Yokozawa , Hiromi Nagaishi
发明人： Masao Hotta , Kenji Maio , Norio Yokozawa , Hiromi Nagaishi
IPC分类号： H03M1/10 , H03M1/00 , H03K13/02
CPC分类号： H03M1/1071 , H03M1/74
摘要： A digital-to-analog conversion system includes a digital-to-analog converter, a source of at least one set of digital input signals and a signal for error compensation and a digital signal for error detection to the converter, a switch to selectively couple either the one set of digital input signals and the signal for error compensation or the signal for error detection to the converter, a clock to generate a switching signal having a predetermined period and duration which is coupled to control the switch, a distribution switch for selectively coupling the output of the digital-to-analog converter to two different terminals, receiving a control input from the clock, a sample and hold circuit to sample and hold the output of the digital-to-analog converter, a detector for detecting a linearity error in the digital-to-analog converter output signal when the digital signal for error detection is coupled as an input thereto, a memory for storing the output of the detector, a circuit to write the output of the detector into the memory, and a circuit to read the data from said memory and couple it as the signal for error compensation at the input to the digital-to-analog converter.
摘要翻译：数模转换系统包括数模转换器，至少一组数字输入信号的源和用于误差补偿的信号以及用于向转换器进行错误检测的数字信号，选择性地耦合一组数字输入信号和用于误差补偿的信号或用于向转换器进行错误检测的信号，产生具有预定周期的切换信号的时钟和耦合以控制开关的持续时间，用于选择性地分配将数模转换器的输出耦合到两个不同的端子，从时钟接收控制输入，采样和保持电路以采样和保持数模转换器的输出，用于检测线性度的检测器当用于错误检测的数字信号作为其输入耦合时，数模转换器输出信号中的误差，用于存储检测器的输出的存储器，用于w 将检测器的输出合并到存储器中，以及电路，用于从所述存储器读取数据，并将其作为用于在数模转换器的输入处的误差补偿信号。

10. 发明授权

US09157990B2 Ultrasonic transmitting/receiving circuit and ultrasonic diagnostic apparatus 有权
标题翻译：超声波发射/接收电路和超声波诊断仪
公开(公告)号：US09157990B2
公开(公告)日：2015-10-13
申请号：US13254657
申请日：2010-03-01
申请人： Atsushi Suzuki , Mitsuhiro Oshiki , Kanako Hatayama , Kenji Maio
发明人： Atsushi Suzuki , Mitsuhiro Oshiki , Kanako Hatayama , Kenji Maio
IPC分类号： G01S7/52 , A61B8/00 , G10K11/34 , G01N29/24
CPC分类号： G01S7/52079 , A61B8/4444 , A61B8/54 , A61B8/56 , B06B2201/76 , G01N29/24 , G01N2291/106 , G01S7/52017 , G10K11/341
摘要： An ultrasonic transmitting/receiving circuit equipped with: a semiconductor circuit element which comprises at least three terminals including a first terminal connected to a plurality of transducer elements that constitute an ultrasonic probe, a second terminal connected to a transmission signal generating circuit, and a third terminal serving as an output terminal of an amplifier of a reception signal from the transducer element, and which has a function of amplifying a signal inputted from one terminal by the other terminal and outputting the amplified signal between at least two terminals among the above-said three terminals; and a control unit which performs control so as to cause the semiconductor circuit element to perform a first function of functioning as a switch for inputting a transmission signal to the transducer element and a second function of amplifying the reception signal received from the transducer element.
摘要翻译：一种超声波发射/接收电路，配备有：半导体电路元件，其包括至少三个端子，包括连接到构成超声波探头的多个换能器元件的第一端子，连接到发送信号发生电路的第二端子和第三端子作为来自换能器元件的接收信号的放大器的输出端子，其具有放大由另一端子从一个端子输入的信号的功能，并且在上述的至少两个端子之间输出放大的信号三个终端; 以及控制单元，其执行控制以使半导体电路元件执行用作向换能器元件输入发送信号的开关的第一功能和放大从换能器元件接收的接收信号的第二功能。

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