专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06380027B2 Dual tox trench dram structures and process using V-groove 失效
标题翻译：双毒tox沟结构和工艺采用V型槽
公开(公告)号：US06380027B2
公开(公告)日：2002-04-30
申请号：US09225127
申请日：1999-01-04
申请人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
发明人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
IPC分类号： H01L21242
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829 , H01L27/10894
摘要： A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.
摘要翻译：用于在衬底上同时形成阵列结构和支撑结构的结构和方法包括：形成阵列结构以具有V形槽，形成支撑结构以具有平坦表面，同时在V形槽中形成第一氧化物，以及其中所述第一氧化物比所述第二氧化物厚。

2. 发明授权

US6153902A Vertical DRAM cell with wordline self-aligned to storage trench 有权
标题翻译：垂直DRAM单元与字线自对准到存储沟槽
公开(公告)号：US6153902A
公开(公告)日：2000-11-28
申请号：US374687
申请日：1999-08-16
申请人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
发明人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/78 , H01L33/00
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译：动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。信号传送装置包括耦合到信号存储节点并从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域沿着沟槽的侧壁在第一扩散区域和第二扩散区域之间延伸的沟道区域，沿着从第一扩散区域延伸到第二扩散区域的沟槽的侧壁形成的栅极绝缘体，填充沟槽的栅极导体并且具有顶表面和字线，其具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

3. 发明授权

US06255158B1 Process of manufacturing a vertical dynamic random access memory device 失效
标题翻译：制造垂直动态随机存取存储器件的过程
公开(公告)号：US06255158B1
公开(公告)日：2001-07-03
申请号：US09667652
申请日：2000-09-22
申请人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
发明人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffision region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译：动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。信号传送装置包括耦合到信号存储节点并且从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域，在所述第一扩散区域和所述第二扩散区域之间沿着所述沟槽的侧壁延伸的沟道区域，沿着从所述第一扩散区域延伸到所述第二扩散区域的所述沟槽的侧壁形成的栅极绝缘体，填充所述沟槽的栅极导体，具有顶表面，并且字线具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

4. 发明授权

US06555891B1 SOI hybrid structure with selective epitaxial growth of silicon 有权
公开(公告)号：US06555891B1
公开(公告)日：2003-04-29
申请号：US09690674
申请日：2000-10-17
申请人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
发明人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
IPC分类号： H01L2900
CPC分类号： H01L27/10894 , H01L21/76262 , H01L21/76264 , H01L21/76278 , H01L21/84 , H01L27/10861 , H01L27/1207
摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

5. 发明授权

US06635543B2 SOI hybrid structure with selective epitaxial growth of silicon 失效
标题翻译：具有硅选择性外延生长的SOI混合结构
公开(公告)号：US06635543B2
公开(公告)日：2003-10-21
申请号：US10335652
申请日：2002-12-31
申请人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
发明人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
IPC分类号： A01L21331
CPC分类号： H01L27/10894 , H01L21/76262 , H01L21/76264 , H01L21/76278 , H01L21/84 , H01L27/10861 , H01L27/1207
摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.
摘要翻译：一种用于在形成于绝缘体上硅（SOI）结构中的沟槽中选择性地生长外延硅的方法和结构。 SOI结构包括在体硅衬底上的掩埋氧化物层（BOX）和BOX上的硅层。衬垫层形成在硅层上。焊盘层包括衬垫氧化物（例如，二氧化硅）上的衬垫氮化物（例如，氮化硅），并且衬垫氧化物已经形成在硅层上。通过各向异性地蚀刻通过焊盘层，硅层，BOX以及体硅衬底内的深度形成沟槽。绝缘垫片形成在沟槽的侧壁上。在沟槽中从沟槽的底部到焊盘层的上方生长外延硅层。去除衬垫层和外延层的部分（例如，通过化学机械抛光），导致外延层的平坦化顶表面与硅层的顶表面大致共面。电子器件可以形成在沟槽的外延硅内。这样的电子设备可以包括对浮体效应敏感的动态随机存取存储器（DRAM），双极晶体管，互补金属氧化物半导体（CMOS）电路以及需要阈值电压匹配的器件。半导体器件（例如，场效应晶体管）可以耦合到沟槽外部的SOI结构。

6. 发明授权

US06396120B1 Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application 失效
标题翻译：硅抗熔丝结构，绝缘体上的体和硅绝缘体制造方法和应用
公开(公告)号：US06396120B1
公开(公告)日：2002-05-28
申请号：US09527191
申请日：2000-03-17
申请人： Claude L Bertin , Toshiharu Furukawa , Erik L. Hedberg , Jack A. Mandelman , William R. Tonti , Richard Q. Williams
发明人： Claude L Bertin , Toshiharu Furukawa , Erik L. Hedberg , Jack A. Mandelman , William R. Tonti , Richard Q. Williams
IPC分类号： H01L2972
CPC分类号： H01L29/78696 , H01L21/823412 , H01L21/823456 , H01L23/5252 , H01L27/10897 , H01L27/1203 , H01L29/42384 , H01L2924/0002 , H01L2924/00
摘要： A method and semiconductor structure that uses a field enhanced region where the oxide thickness is substantially reduced, thereby allowing antifuse programming at burn-in voltages which do not damage the standard CMOS logic. The semiconductor device comprises a substrate that has a raised protrusion terminating at a substantially sharp point, an insulator layer over the raised protrusion sufficiently thin to be breached by a breakdown voltage applied to the sharp point, a region comprised of a material on the insulator over the raised protrusion for becoming electrically coupled to the substrate after the insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to the substrate. In a second embodiment, the semiconductor device comprises a substrate having a trough formed in a top surface of the substrate, a relatively thick insulator layer over the top surface of the substrate, a relatively thin insulator layer over the trough that is breached by a breakdown voltage applied to the trough, a region comprised of a material on the relatively thin insulator layer over the trough for becoming electrically coupled to the substrate after the relatively thin insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to said substrate.
摘要翻译：一种使用场强增强区域的方法和半导体结构，其中氧化物厚度大大降低，从而允许在不损坏标准CMOS逻辑的老化电压下进行反熔丝编程。半导体器件包括具有突出的突起终止于基本尖锐点的衬底，凸起突起上的绝缘体层足够薄以致被施加到尖锐点的击穿电压所破坏，由绝缘体上的材料构成的区域在绝缘体层被击穿电压破坏之后用于电耦合到衬底的凸起突起，以及用于向衬底提供击穿电压的触点。在第二实施例中，半导体器件包括在衬底的顶表面中形成有槽的衬底，在衬底的顶表面上方的相对较厚的绝缘体层，在槽的相对较薄的绝缘体层，其被破坏电压施加到槽，由比较薄的绝缘体层上的材料组成的区域，该沟槽在相对较薄的绝缘体层被击穿电压破坏之后用于变成与电极耦合的衬底;以及用于将击穿电压提供给所述基板。

7. 发明授权

US06271080B1 Structure and method for planar MOSFET DRAM cell free of wordline gate conductor to storage trench overlay sensitivity 失效
标题翻译：平面MOSFET DRAM单元的结构和方法没有字线栅极导体与存储沟槽覆盖灵敏度
公开(公告)号：US06271080B1
公开(公告)日：2001-08-07
申请号：US09465109
申请日：1999-12-16
申请人： Jack A. Mandelman , Toshiharu Furukawa , William R. Tonti
发明人： Jack A. Mandelman , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10861 , H01L27/10873
摘要： A memory cell (8F2 and sub-8F2) formed by: (a) forming a stack of at least four material layers on a surface of a semiconductor substrate, wherein at least two of said material layers of said stack are selectively etchable relative to each other; (b) patternwise etching through said stack to define a critical pattern of remaining stack and spaces where said semiconductor substrate is exposed, said critical pattern defining possible locations for trench capacitors and gate conductors; (c) filling said spaces with a filler material which is selectively etchable relative to a topmost layer of said remaining stack; (d) planarizing the filler material stopping at said topmost layer of said remaining stack; (e) forming trench capacitors in said semiconductor substrate by etching through portions of said filler material and said substrate, wherein said etching removes a portion of said topmost layer of said remaining stack and exposes a portion of a layer of said stack that is next to the topmost layer; (f) planarizing the remaining portion of said stack and filler material to remove the remaining portion of the topmost layer of said stack and the remaining portion of the layer that is next to the topmost layer and thereby exposing a layer of said stack that is second from the topmost layer; (g) replacing at least a portion of either said remaining stack and/or remaining filler material with a placeholder material corresponding to locations for gate conductors; and (h) forming said gate conductors and remaining portions of said transistors, bitlines and wordlines of said memory cell.
摘要翻译：通过以下步骤形成的存储器单元（8F2和sub-8F2）：（a）在半导体衬底的表面上形成至少四个材料层的堆叠，其中所述堆叠的至少两个所述材料层相对于每个其他; （b）通过所述堆叠进行图案蚀刻以限定所述半导体衬底暴露的剩余堆叠和空间的临界图案，所述临界图案限定了沟槽电容器和栅极导体的可能位置; （c）用相对于所述剩余堆叠的最上层选择性地蚀刻的填充材料填充所述空间; （d）使在所述剩余堆叠的所述最上层停止的填充材料平坦化; （e）通过蚀刻穿过所述填充材料和所述衬底的部分在所述半导体衬底中形成沟槽电容器，其中所述蚀刻去除所述剩余堆叠的所述最上层的一部分，并且暴露所述堆叠层的下一部分的一部分最上层; （f）使所述堆叠和填充材料的剩余部分平坦化，以去除所述堆叠的最上层的剩余部分和邻近最上层的层的剩余部分，从而暴露出第二层的所述堆叠层从最上层; （g）用对应于栅极导体的位置的占位符材料代替所述剩余堆叠和/或剩余填充材料的至少一部分; 和（h）形成所述晶体管的所述栅极导体和剩余部分，所述存储单元的位线和字线。

8. 发明授权

US5773362A Method of manufacturing an integrated ULSI heatsink 失效
标题翻译：制造集成ULSI散热器的方法
公开(公告)号：US5773362A
公开(公告)日：1998-06-30
申请号：US838539
申请日：1997-04-09
申请人： William R. Tonti , Jack A. Mandelman , Jerzy M. Zalesinski , Toshiharu Furukawa , Son V. Nguyen , Dureseti Chidambarrao
发明人： William R. Tonti , Jack A. Mandelman , Jerzy M. Zalesinski , Toshiharu Furukawa , Son V. Nguyen , Dureseti Chidambarrao
IPC分类号： H01L21/60 , H01L23/367 , H01L29/06 , H01L29/34 , H01L21/44
CPC分类号： H01L24/27 , H01L23/367 , H01L24/32 , H01L24/83 , H01L29/0657 , H01L29/34 , H01L2224/03505 , H01L2224/04026 , H01L2224/16225 , H01L2224/16227 , H01L2224/32057 , H01L2224/32059 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/8319 , H01L2224/83385 , H01L2224/83801 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10158 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/181 , Y10S438/928 , Y10S438/964
摘要： A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips. The heatsink itself is prepared by first optionally roughening the surface and metalizing the backside of the heatsink with metal interlayer. Next, the chip is thermally attached to the heatsink by reflowing the thermally conductive reflowable material.
摘要翻译：简单且低成本的ULSI集成散热器通过将散热材料集成到硅晶片中更有效地从硅封装中去除热量，将现有的二维技术转化为三维。高功率集成ULSI封装和散热器的制造开始于制造集成电路晶片，直到将晶片切割成单个芯片。晶片的正面受到保护，而晶片的背面露出。暴露的背面通过化学和/或机械过程粗糙化。任选地，然后执行吸气过程以除去杂质。然后用金属夹层涂覆粗糙的背面，优选用铬（Cr）形成铝（Al）。一层铜（Cu）任选地涂覆在金属夹层上。高度导电的可回流材料，例如焊料或金共晶，沉积在金属夹层上。此时，晶片被切割成芯片。散热器本身通过首先任选地使表面粗糙化并用金属中间层金属化散热器的背面来制备。接下来，通过回流导热的可回流材料将芯片热连接到散热器。

9. 发明授权

US5729052A Integrated ULSI heatsink 失效
标题翻译：集成ULSI散热器
公开(公告)号：US5729052A
公开(公告)日：1998-03-17
申请号：US667210
申请日：1996-06-20
申请人： William R. Tonti , Jack A. Mandelman , Jerzy M. Zalesinski , Toshiharu Furukawa , Son V. Nguyen , Dureseti Chidambarrao
发明人： William R. Tonti , Jack A. Mandelman , Jerzy M. Zalesinski , Toshiharu Furukawa , Son V. Nguyen , Dureseti Chidambarrao
IPC分类号： H01L21/60 , H01L23/367 , H01L29/06 , H01L29/34 , H01L23/34
CPC分类号： H01L24/27 , H01L23/367 , H01L24/32 , H01L24/83 , H01L29/0657 , H01L29/34 , H01L2224/03505 , H01L2224/04026 , H01L2224/16225 , H01L2224/16227 , H01L2224/32057 , H01L2224/32059 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/8319 , H01L2224/83385 , H01L2224/83801 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10158 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/181 , Y10S438/928 , Y10S438/964
摘要： A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) followed by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips. The heatsink itself is prepared by first optionally roughening the surface and metalizing the backside of the heatsink with metal interlayer. Next, the chip is thermally attached to the heatsink by reflowing the thermally conductive reflowable material.
摘要翻译：简单且低成本的ULSI集成散热器通过将散热材料集成到硅晶片中更有效地从硅封装中去除热量，将现有的二维技术转化为三维。高功率集成ULSI封装和散热器的制造开始于制造集成电路晶片，直到将晶片切割成单个芯片。晶片的正面受到保护，而晶片的背面露出。暴露的背面通过化学和/或机械过程粗糙化。任选地，然后执行吸气过程以除去杂质。然后将粗糙的背面涂覆有金属中间层，优选铝（Al），随后涂覆铬（Cr）。一层铜（Cu）任选地涂覆在金属夹层上。高度导电的可回流材料，例如焊料或金共晶，沉积在金属夹层上。此时，晶片被切割成芯片。散热器本身通过首先任选地使表面粗糙化并用金属中间层金属化散热器的背面来制备。接下来，通过回流导热的可回流材料将芯片热连接到散热器。

10. 发明授权

US07217604B2 Structure and method for thin box SOI device 有权
标题翻译：薄盒SOI器件的结构和方法
公开(公告)号：US07217604B2
公开(公告)日：2007-05-15
申请号：US10906014
申请日：2005-01-31
申请人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
发明人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78606 , H01L29/78612
摘要： A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.
摘要翻译：一种形成半导体器件的方法，包括在所述衬底的表面上提供具有第一绝缘层的衬底以及在所述第一绝缘层的表面上的器件层，在所述第一绝缘层和所述器件层周围形成间隔物，在衬底的第一区域和不相邻的第二区域中移除邻近第一绝缘层的衬底的一部分，使得在衬底的第一和第二区域中形成开口，使衬底与第一绝缘层相邻，在衬底的第三区域中的绝缘层，填充衬底的第一和第二区域内的开口，使器件的表面平坦化，以及在器件层内形成器件，使得器件的扩散区域形成在器件层在衬底的第一和第二区域之上，并且器件的沟道区形成在衬底的第三区域上方。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式