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    • 10. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08711632B2
    • 2014-04-29
    • US13425860
    • 2012-03-21
    • Akira Katayama
    • Akira Katayama
    • G11C11/34
    • G11C11/1673
    • The control circuit selects, as the first reference cell, the first memory cell having a maximum reading current supplied by turning on the first select transistor in a state in which resistance values of the first memory cells are all increased. The control circuit selects, as the second reference cell, the second memory cell having a maximum reading current supplied by turning on the second select transistor in a state in which resistance values of the second memory cells are all increased. The first reference-current setting circuit sets, as the first reference current, a current obtained by adding a first adjusting current to the reading current of the first reference cell. The second reference-current setting circuit sets, as the second reference current, a current obtained by adding a second adjusting current to the reading current of the second reference cell.
    • 控制电路在第一存储单元的电阻值全部增加的状态下选择具有通过接通第一选择晶体管而提供的最大读取电流的第一存储单元作为第一参考单元。 控制电路在第二存储单元的电阻值全部增加的状态下选择具有通过接通第二选择晶体管而提供的最大读取电流的第二存储单元作为第二参考单元。 第一参考电流设置电路将通过将第一调整电流加到第一参考单元的读取电流而获得的电流作为第一参考电流。 第二基准电流设定电路将通过将第二调整电流加到第二参考单元的读取电流而获得的电流作为第二参考电流。