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1. 发明申请

US20100242108A1 METHOD AND SYSTEM FOR MEMORY PROTECTION AND SECURITY USING CREDENTIALS 失效
标题翻译：使用证书的内存保护和安全的方法和系统
公开(公告)号：US20100242108A1
公开(公告)日：2010-09-23
申请号：US12792766
申请日：2010-06-03
申请人： Michael Backes , Shmuel Ben-Yehuda , Jan Leonhard Camenisch , Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III , Michael Waidner
发明人： Michael Backes , Shmuel Ben-Yehuda , Jan Leonhard Camenisch , Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III , Michael Waidner
IPC分类号： G06F21/00 , G06F12/14
CPC分类号： G06F12/1433 , G06F12/1441 , G06F12/1466
摘要： A computer-implemented system and method for protecting a memory are provided. The system includes a memory section with privileged and non-privileged sections, a host gateway (HG) to generate a capability credential, a device controller (DC) to append the credential to data transmitted to the memory, and at least one IO device enabled to do direct memory access (DMA) transactions with the memory.
摘要翻译：提供了一种用于保护存储器的计算机实现的系统和方法。该系统包括具有特权和非特权部分的存储器部分，用于生成能力证书的主机网关（HG），将证书附加到传输到存储器的数据的设备控制器（DC），以及启用的至少一个IO设备与内存进行直接内存访问（DMA）事务。

2. 发明授权

US08650406B2 Memory protection and security using credentials 有权
标题翻译：内存保护和安全使用凭证
公开(公告)号：US08650406B2
公开(公告)日：2014-02-11
申请号：US13405367
申请日：2012-02-27
申请人： Michael Backes , Shmuel S Ben-Yehuda , Jan Leonhard Camenisch , Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III , Michael Waidner
发明人： Michael Backes , Shmuel S Ben-Yehuda , Jan Leonhard Camenisch , Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III , Michael Waidner
IPC分类号： G06F12/14 , G06F13/16
CPC分类号： G06F12/1433 , G06F12/1441 , G06F12/1466
摘要： A computer-implemented system and method for protecting a memory are provided. The system includes a memory section with privileged and non-privileged sections, a host gateway (HG) to generate a capability credential, a device controller (DC) to append the credential to data transmitted to the memory, and at least one IO device enabled to do direct memory access (DMA) transactions with the memory.
摘要翻译：提供了一种用于保护存储器的计算机实现的系统和方法。该系统包括具有特权和非特权部分的存储器部分，用于生成能力证书的主机网关（HG），将证书附加到传输到存储器的数据的设备控制器（DC），以及启用的至少一个IO设备与内存进行直接内存访问（DMA）事务。

3. 发明授权

US07925801B2 Method and system for protection and security of IO devices using credentials 有权
标题翻译：使用凭证的IO设备的保护和安全的方法和系统
公开(公告)号：US07925801B2
公开(公告)日：2011-04-12
申请号：US11333716
申请日：2006-01-17
申请人： Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III
发明人： Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F21/85 , G06Q20/3821
摘要： A method and system for protection and security of IO devices using credential are provided. The system may include at least one consumer arranged to initiate IO requests from the IO device, and the IO requests may include IO capability allocation and additional parameters. The system may also include an IO resource manager (IORM) arranged to translate the IO capability allocation and additional parameters included in said IO request to a set of capability tokens for the consumer or for a group of consumers, to generate a global key to protect the capability tokens, and further arranged to manage the IO device. The system may further include a channel component arranged to transfer and receive the IO request to and from the IO device.
摘要翻译：提供了使用凭证的IO设备的保护和安全性的方法和系统。该系统可以包括至少一个消费者，被安排为从IO设备发起IO请求，并且IO请求可以包括IO能力分配和附加参数。该系统还可以包括IO资源管理器（IORM），其被配置为将IO能力分配和包括在所述IO请求中的附加参数转换成消费者或一组消费者的一组能力令牌以产生保护的全局密钥能力标记，并进一步安排管理IO设备。该系统还可以包括被配置为向IO设备传送和接收IO请求的信道组件。

4. 发明申请

US20120159610A1 MEMORY PROTECTION AND SECURITY USING CREDENTIALS 有权
标题翻译：使用证书的内存保护和安全
公开(公告)号：US20120159610A1
公开(公告)日：2012-06-21
申请号：US13405367
申请日：2012-02-27
申请人： Michael Backes , Shmuel Ben-Yehuda , Jan Leonhard Camenisch , Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III , Michael Waidner
发明人： Michael Backes , Shmuel Ben-Yehuda , Jan Leonhard Camenisch , Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III , Michael Waidner
IPC分类号： G06F21/00 , G06F13/28
CPC分类号： G06F12/1433 , G06F12/1441 , G06F12/1466
摘要： A computer-implemented system and method for protecting a memory are provided. The system includes a memory section with privileged and non-privileged sections, a host gateway (HG) to generate a capability credential, a device controller (DC) to append the credential to data transmitted to the memory, and at least one IO device enabled to do direct memory access (DMA) transactions with the memory.
摘要翻译：提供了一种用于保护存储器的计算机实现的系统和方法。该系统包括具有特权和非特权部分的存储器部分，用于生成能力证书的主机网关（HG），将证书附加到传输到存储器的数据的设备控制器（DC），以及启用的至少一个IO设备与内存进行直接内存访问（DMA）事务。

5. 发明授权

US07757280B2 Method and system for memory protection and security using credentials 失效
标题翻译：用于内存保护和安全使用凭证的方法和系统
公开(公告)号：US07757280B2
公开(公告)日：2010-07-13
申请号：US11333066
申请日：2006-01-17
申请人： Michael Backes , Shmuel Ben-Yehuda , Jan Leonhard Camenisch , Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III , Michael Waidner
发明人： Michael Backes , Shmuel Ben-Yehuda , Jan Leonhard Camenisch , Ton Engbersen , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III , Michael Waidner
IPC分类号： G06F21/00 , H04L12/14
CPC分类号： G06F12/1433 , G06F12/1441 , G06F12/1466
摘要： A computer-implemented method for protecting a memory is provided. The method includes responsive to a direct memory access (DMA) request received from a consumer for a transaction of data from an IO device to the memory, the request including an IO command and a capability (CAP), generating a cryptographically signed capability (CAPB), forming a credential from CAP and CAPB, appending the credential to the IO command, configuring the IO device according to the credential and the IO command, transmitting the data from the IO device to the memory and prior to allowing execution of the DMA, authenticating that the credential is valid, further includes regenerating CAPB from a key available to an authenticating entity and from the CAP (included in CAPB) and verifying that the memory region information described in the cryptographically signed capability is the same as the requested region that was originally created, and that the cryptographically signed capability encompasses the IO command.
摘要翻译：提供了一种用于保护存储器的计算机实现的方法。该方法包括响应于从消费者接收的用于从IO设备到存储器的数据交易的直接存储器访问（DMA）请求，该请求包括IO命令和能力（CAP），生成加密签名的能力（CAPB ），从CAP和CAPB形成证书，将凭证附加到IO命令，根据凭证和IO命令配置IO设备，将数据从IO设备发送到存储器，并且在允许执行DMA之前，认证证书是有效的，还包括从认证实体和CAP（包括在CAPB中）的可用密钥中重新生成CAPB，并验证以加密签名能力描述的存储器区域信息是否与被请求的区域相同最初创建，并且加密签名的功能包含IO命令。

6. 发明授权

US08949569B2 Enhanced direct memory access 有权
标题翻译：增强的直接内存访问
公开(公告)号：US08949569B2
公开(公告)日：2015-02-03
申请号：US12111968
申请日：2008-04-30
申请人： Alan Frederic Benner , Shmuel Ben-Yehuda , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III
发明人： Alan Frederic Benner , Shmuel Ben-Yehuda , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III
IPC分类号： G06F9/26 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3851 , G06F9/3824 , G06F12/0877 , G06F12/0891
摘要： A method for facilitating direct memory access in a computing system in response to a request to transfer data is provided. The method comprises selecting a thread for transferring the data, wherein the thread executes on a processing core within the computing system; providing the thread with the request, wherein the request comprises information for carrying out a data transfer; and transferring the data according to the request. The method may further comprise: coordinating the request with a memory management unit, such that virtual addresses may be used to transfer data; invalidating a cache line associated with the source address or flushing a cache line associated with the destination address, if requested. Multiple threads can be selected to transfer data based on their proximity to the destination address.
摘要翻译：提供了一种用于响应于传送数据的请求而促进计算系统中的直接存储器访问的方法。该方法包括选择用于传送数据的线程，其中线程在计算系统内的处理核上执行; 向所述线程提供所述请求，其中所述请求包括用于执行数据传送的信息; 并根据请求传送数据。该方法还可以包括：将请求与存储器管理单元协调，使得可以使用虚拟地址来传送数据; 如果请求，则使与源地址相关联的高速缓存行无效或者刷新与目的地地址相关联的高速缓存行。可以选择多个线程以根据其到目的地地址的接近度传输数据。

7. 发明申请

US20090276571A1 Enhanced Direct Memory Access 有权
标题翻译：增强的直接内存访问
公开(公告)号：US20090276571A1
公开(公告)日：2009-11-05
申请号：US12111968
申请日：2008-04-30
申请人： Alan Frederic Benner , Shmuel Ben-Yehuda , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III
发明人： Alan Frederic Benner , Shmuel Ben-Yehuda , Zorik Machulsky , Julian Satran , Leah Shalev , Ilan Shimony , Thomas Basil Smith, III
IPC分类号： G06F9/30 , G06F12/00
CPC分类号： G06F9/3851 , G06F9/3824 , G06F12/0877 , G06F12/0891
摘要： A method for facilitating direct memory access in a computing system in response to a request to transfer data is provided. The method comprises selecting a thread for transferring the data, wherein the thread executes on a processing core within the computing system; providing the thread with the request, wherein the request comprises information for carrying out a data transfer; and transferring the data according to the request. The method may further comprise: coordinating the request with a memory management unit, such that virtual addresses may be used to transfer data; invalidating a cache line associated with the source address or flushing a cache line associated with the destination address, if requested. Multiple threads can be selected to transfer data based on their proximity to the destination address.
摘要翻译：提供了一种用于响应于传送数据的请求而促进计算系统中的直接存储器访问的方法。该方法包括选择用于传送数据的线程，其中线程在计算系统内的处理核上执行; 向所述线程提供所述请求，其中所述请求包括用于执行数据传送的信息; 并根据请求传送数据。该方法还可以包括：将请求与存储器管理单元协调，使得可以使用虚拟地址来传送数据; 如果请求，则使与源地址相关联的高速缓存行无效或者刷新与目的地地址相关联的高速缓存行。可以选择多个线程以根据其到目的地地址的接近度传输数据。

8. 发明授权

US07739474B2 Method and system for unifying memory access for CPU and IO operations 失效
标题翻译：用于统一CPU和IO操作的内存访问的方法和系统
公开(公告)号：US07739474B2
公开(公告)日：2010-06-15
申请号：US11348805
申请日：2006-02-07
申请人： Antonius Paulus Engbersen , Julian Satran , Edi Shmueli , Thomas Basil Smith, III
发明人： Antonius Paulus Engbersen , Julian Satran , Edi Shmueli , Thomas Basil Smith, III
IPC分类号： G06F9/26
CPC分类号： G06F12/1483
摘要： A system and method for unifying access to a physical memory by operations using virtual addresses of the same virtual address space are provided. The operations may be generated by at least one central processing unit (CPU operations) and/or by at least one IO device (IO operations). The system may include a bus arranged to transfer data and virtual addresses of the same virtual address space from the central processing unit (CPU) and the IO device to a unified memory management unit (UMMU), a unified memory management unit (UMMU) arranged to translate the virtual addresses to physical addresses, and to protect the physical memory from illegal access attempts of the CPU operations and the IO operations. The system may further include a memory controller arranged to manage access to the physical memory. The access is done by using physical addresses.
摘要翻译：提供了通过使用相同虚拟地址空间的虚拟地址的操作来统一访问物理存储器的系统和方法。操作可以由至少一个中央处理单元（CPU操作）和/或至少一个IO设备（IO操作）生成。系统可以包括布置成将来自中央处理单元（CPU）和IO设备的相同虚拟地址空间的数据和虚拟地址传输到统一存储器管理单元（UMMU）的总线，布置在统一存储器管理单元（UMMU）将虚拟地址转换为物理地址，并保护物理内存免受CPU操作和IO操作的非法访问尝试。系统还可以包括布置成管理对物理存储器的访问的存储器控制器。访问通过使用物理地址完成。

9. 发明授权

US06766429B1 Low cost and high RAS mirrored memory 失效
标题翻译：低成本和高RAS镜像记忆
公开(公告)号：US06766429B1
公开(公告)日：2004-07-20
申请号：US09652752
申请日：2000-08-31
申请人： Patrick Maurice Bland , Thomas Basil Smith, III , Robert Brett Tremaine , Michael Edward Wazlowski
发明人： Patrick Maurice Bland , Thomas Basil Smith, III , Robert Brett Tremaine , Michael Edward Wazlowski
IPC分类号： G06F1200
CPC分类号： G06F11/1666 , G06F11/20 , G06F12/023 , G06F12/0292 , G06F2212/401
摘要： An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank. After a memory bank is identified as faulty, the memory controller precludes further read access to the bank, permitting replacement without interruption to the application or operating system software operation.
摘要翻译：具有存储器压缩的数据处理系统的结构，方法和装置以及形成单个统一存储器的两个公共存储器或能够在存在硬件故障或冗余“双工”计算机维护中断时能够连续操作的双存储器系统，而不需要复制存储器件的成本。存储器控制器采用硬件存储器压缩以将存储器需求减少一半，这补偿了冗余存储器所需的存储器的倍增。存储器控制器采用错误检测和校正码，用于在读取访问期间检测存储子系统故障。在检测到故障时，硬件自动将读访问重新发送到逻辑上与故障库相同的单独的存储体。在存储器被识别为故障之后，存储器控制器排除对存储体的进一步读取访问，允许更换而不中断应用程序或操作系统软件操作。

10. 发明授权

US06339813B1 Memory system for permitting simultaneous processor access to a cache line and sub-cache line sectors fill and writeback to a system memory 失效
标题翻译：用于允许同时处理器访问高速缓存行和子高速缓存行扇区的存储器系统填充和回写到系统存储器
公开(公告)号：US06339813B1
公开(公告)日：2002-01-15
申请号：US09480702
申请日：2000-01-07
申请人： Thomas Basil Smith, III , Robert Brett Tremaine
发明人： Thomas Basil Smith, III , Robert Brett Tremaine
IPC分类号： G06F1314
CPC分类号： G06F12/0859
摘要： In a cache memory system, a mechanism enabling two logical cache lines to coexist within the same physical cache line, during line fill and replacement, thus minimizing the likelihood of stalling accesses to the cache while the line is being filled or replaced. A control mechanism governs access to the cache line and tracks which sub-cache line units contain old or new data, or are empty during the fill/replacement procedure. The control mechanism thus maintains a sub-cache line state for the purpose of permitting a processor to gain access to a portion of the cache line before it is completely filled or replaced.
摘要翻译：在高速缓冲存储器系统中，在行填充和替换期间，能够使两个逻辑高速缓存行在同一物理高速缓存行内共存的机制，从而最小化在线被填充或替换时停止对高速缓存的访问的可能性。控制机制控制对高速缓存行的访问，并跟踪哪些子高速缓存行单元包含旧数据或新数据，或者在填充/替换过程期间为空。因此，控制机制保持子高速缓存线路状态，以便允许处理器在完全填充或替换之前获得对高速缓存行的一部分的访问。

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