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1. 发明授权

US6008674A Semiconductor integrated circuit device with adjustable high voltage detection circuit 失效
标题翻译：具有可调高压检测电路的半导体集成电路器件
公开(公告)号：US6008674A
公开(公告)日：1999-12-28
申请号：US927796
申请日：1997-09-11
申请人： Tomohisa Wada , Masaaki Mihara , Yasuhiko Taito , Yoshikazu Miyawaki , Katsumi Dosaka
发明人： Tomohisa Wada , Masaaki Mihara , Yasuhiko Taito , Yoshikazu Miyawaki , Katsumi Dosaka
IPC分类号： G11C16/06 , G05F1/56 , G05F3/24 , G11C5/14 , G11C11/407 , H03K5/153
CPC分类号： G11C5/147 , G05F3/242
摘要： A semiconductor integrated circuit device with a high voltage detection circuit comprises a high voltage step-down circuit for stepping down a high voltage input and outputting the stepped-down voltage, a reference voltage generator for generating plural reference voltages, a reference voltage selector for selecting one of the plural reference voltages, a high voltage detection circuit for comparing the stepped down voltage with the selected reference voltage to detect a high voltage and a control circuit for controlling the voltage drop of the high voltage and selection of the plural reference voltages to set the high voltage to be detected by the high voltage detector. There is also disclosed semiconductor integrated circuit having a high voltage step-down circuit for outputting plural stepped-down voltages having a fine tuner for fine-tuning each of the plural stepped-down voltages wherein a stepped-down voltage having been tuned finely is compared with a reference voltage given by a reference voltage generator.
摘要翻译：具有高电压检测电路的半导体集成电路装置包括用于降压高压输入并输出降压的高压降压电路，用于产生多个参考电压的参考电压发生器，用于选择的参考电压选择器多个参考电压中的一个，用于将降压电压与所选择的参考电压进行比较以检测高电压的高电压检测电路，以及用于控制高电压的电压降和选择多个参考电压的控制电路以设置由高电压检测器检测的高电压。还公开了一种具有高压降压电路的半导体集成电路，用于输出具有微调整器的多个降压电压，用于微调多个降压电压中的每一个，其中比较精调的降压电压具有由参考电压发生器给出的参考电压。

2. 发明授权

US5872476A Level converter circuit generating a plurality of positive/negative voltages 失效
标题翻译：电平转换器电路产生多个正/负电压
公开(公告)号：US5872476A
公开(公告)日：1999-02-16
申请号：US716846
申请日：1996-09-10
申请人： Masaaki Mihara , Yasuhiko Taito
发明人： Masaaki Mihara , Yasuhiko Taito
IPC分类号： G11C17/00 , G11C16/06 , H03K3/356 , H03K17/10 , H03K19/0185 , H03L5/00 , H03K19/0175
CPC分类号： H03K3/356113
摘要： A level converter circuit includes a first CVSL (Cascade Voltage Switch Logic) circuit responsive to a voltage switching signal for providing a power supply voltage or an input voltage, and a second CVSL circuit responsive to a voltage equal to the power supply voltage or input voltage output from the first CVSL circuit for providing a positive input voltage or a negative input voltage. The level converter circuit can supply high positive and negative voltages required for a flash memory.
摘要翻译：电平转换器电路包括响应于用于提供电源电压或输入电压的电压切换信号的第一CVSL（级联电压开关逻辑）电路和响应于等于电源电压或输入电压的电压的第二CVSL电路从第一CVSL电路输出，以提供正输入电压或负输入电压。电平转换器电路可以提供闪存所需的高正负电压。

3. 发明授权

US06344766B1 Voltage level converter circuit improved in operation reliability 有权
公开(公告)号：US06344766B1
公开(公告)日：2002-02-05
申请号：US09515594
申请日：2000-02-29
申请人： Masaaki Mihara , Yasuhiko Taito
发明人： Masaaki Mihara , Yasuhiko Taito
IPC分类号： H03K190185
CPC分类号： G11C16/12 , G05F3/247 , G11C5/147
摘要： A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.

4. 发明授权

US6049243A Voltage level converter circuit improved in operation reliability 失效
公开(公告)号：US6049243A
公开(公告)日：2000-04-11
申请号：US45568
申请日：1998-03-23
申请人： Masaaki Mihara , Yasuhiko Taito
发明人： Masaaki Mihara , Yasuhiko Taito
IPC分类号： G11C11/34 , G05F1/56 , G05F3/24 , G11C5/14 , G11C16/06 , G11C16/12 , H03K19/0185
CPC分类号： G11C5/147 , G05F3/247 , G11C16/12
摘要： A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.

5. 发明授权

US06198331B1 Voltage level converter circuit improved in operation reliability 有权
标题翻译：电压转换电路提高了运行可靠性
公开(公告)号：US06198331B1
公开(公告)日：2001-03-06
申请号：US09516212
申请日：2000-02-29
申请人： Masaaki Mihara , Yasuhiko Taito
发明人： Masaaki Mihara , Yasuhiko Taito
IPC分类号： H03K190185
CPC分类号： G11C5/147 , G05F3/247 , G11C16/12
摘要： A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.
摘要翻译：电压电平转换器电路包括第一节点，具有根据输入电压的电压的第二节点，连接在第二节点和第一节点之间的P沟道MOS晶体管，当输入电压达到L电平时导通;第三节点连接在第三节点和第四节点之间的第一N沟道MOS晶体管，当所述输入电压达到H电平时导通;第二N沟道MOS晶体管，连接在所述第一节点和所述第四节点之间，并且具有提供减轻信号的栅极，第三N沟道MOS晶体管和用于根据第一电压的电平提供缓解信号的电平确定电路。

6. 发明申请

US20070226597A1 Semiconductor memory having embedded microcomputer with ECC function 有权
标题翻译：具有ECC功能的嵌入式微型计算机的半导体存储器
公开(公告)号：US20070226597A1
公开(公告)日：2007-09-27
申请号：US11651075
申请日：2007-01-09
申请人： Yasuhiko Taito , Masashi Muto , Eiji Sakuma , Tsukasa Oishi
发明人： Yasuhiko Taito , Masashi Muto , Eiji Sakuma , Tsukasa Oishi
IPC分类号： H03M13/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： There is provided a semiconductor device of which the circuit scale does not significantly increase even with an ECC function. A microcomputer having an internal flash memory inserts one weight in a sense amplifier activation signal only when an error detection signal is on the H level at a given time in a read cycle or when the error detection signal which was on the H level in a previous read cycle has shifted to the L level in a current read cycle. This allows the retrieval of output data signals after waiting till the output data signals through error correction are determined only when an error is contained in the output data signals.
摘要翻译：提供了即使使用ECC功能，电路规模也不显着增加的半导体器件。具有内部闪速存储器的微型计算机仅在读取周期中的给定时间处于错误检测信号处于H电平时或者在前一个时间内处于H电平的错误检测信号时，在读出放大器激活信号中插入一个权重读取周期在当前读取周期中已经转移到L电平。这允许在等待直到通过错误校正的输出数据信号仅在输出数据信号中包含错误时才确定时才检索输出数据信号。

7. 发明授权

US06781431B2 Clock generating circuit 失效
标题翻译：时钟发生电路
公开(公告)号：US06781431B2
公开(公告)日：2004-08-24
申请号：US10349033
申请日：2003-01-23
申请人： Yasuhiko Taito , Akira Yamazaki , Fukashi Morishita , Nobuyuki Fujii , Mihoko Akiyama , Mako Okamoto
发明人： Yasuhiko Taito , Akira Yamazaki , Fukashi Morishita , Nobuyuki Fujii , Mihoko Akiyama , Mako Okamoto
IPC分类号： G06F104
CPC分类号： H03K3/0315 , H02M3/07 , H03K3/013 , H03K3/70
摘要： The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.
摘要翻译：用于产生时钟信号的时钟发生电路包括具有以环形配置连接的奇数个反相器的环形振荡器。当激活信号处于第一电平时，环形振荡器被激活以产生时钟信号，并且当激活信号处于第二电平时被停止产生时钟信号。锁存电路连接到环形振荡器的输出节点，并且响应于激活信号从第一电平到第二电平的转变而保持环形振荡器的输出节点的电平。当激活信号从H电平降低到L电平时，锁存时钟信号的电平，从而防止产生时钟信号中的毛刺。

8. 发明授权

US06501326B2 Semiconductor integrated circuit 失效
公开(公告)号：US06501326B2
公开(公告)日：2002-12-31
申请号：US09849392
申请日：2001-05-07
申请人： Nobuyuki Fujii , Fukashi Morishita , Akira Yamazaki , Yasuhiko Taito , Mako Okamoto
发明人： Nobuyuki Fujii , Fukashi Morishita , Akira Yamazaki , Yasuhiko Taito , Mako Okamoto
IPC分类号： G05F110
CPC分类号： H02M3/073 , G05F1/465
摘要： A capacitor (C12) is connected between a node (L) in a double boost part and the ground, and the amplitude of a repetitive pulse from the node (L) is made less than twice that of the power-supply voltage through utilization of charge and discharge of the capacitor (C12).

9. 发明申请

US20080225592A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080225592A1
公开(公告)日：2008-09-18
申请号：US12073834
申请日：2008-03-11
申请人： Yasuhiko Taito , Naoki Otani , Tomohisa Iba , Tsukasa Oishi
发明人： Yasuhiko Taito , Naoki Otani , Tomohisa Iba , Tsukasa Oishi
IPC分类号： G11C5/02
CPC分类号： G11C16/16 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： With this flash memory, because a plurality of memory blocks are formed on a surface of a single P-type well, a layout area can be made small. Further, when erasing data for a memory block to be erased, a voltage of the P-type well is applied to all word lines of a memory block to be not erased. Consequently, the voltage of the P-type well and the voltage of all word lines of the memory block to be not erased change at the same time. With this, it is possible to prevent a threshold voltage for the memory block to be not erased from changing.
摘要翻译：利用该闪速存储器，由于在单个P型阱的表面上形成多个存储块，因此可以使布局区域变小。此外，当擦除要擦除的存储块的数据时，P型阱的电压被施加到存储块的所有字线以便不被擦除。因此，P型阱的电压和不被擦除的存储器块的所有字线的电压同时变化。由此，可以防止存储块的阈值电压不被擦除。

10. 发明授权

US07251165B2 Semiconductor flash memory 有权
标题翻译：半导体闪存
公开(公告)号：US07251165B2
公开(公告)日：2007-07-31
申请号：US10930873
申请日：2004-09-01
申请人： Yasuhiko Taito , Naoki Otani , Kayoko Omoto , Kenji Koda
发明人： Yasuhiko Taito , Naoki Otani , Kayoko Omoto , Kenji Koda
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/3495 , G11C16/3418 , G11C16/349
摘要： A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.
摘要翻译：半导体闪速存储器包括擦除/写入控制单元，当执行读取存储器单元的擦除/写入操作时，读取和检测每个存储单元的读取的存储器单元的存储器电流，并且调整每个读取存储器的阈值电压以及读出控制单元，当执行读取操作时，从擦除/写入控制单元存储相同数据的读取存储器单元中同时选择至少两个读取存储单元，并且感测总存储器用于至少两个读存储器单元的电流。

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