专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5886388A Static semiconductor memory device and manufacturing method thereof 失效
标题翻译：静态半导体存储器件及其制造方法
公开(公告)号：US5886388A
公开(公告)日：1999-03-23
申请号：US10473
申请日：1998-01-21
申请人： Tomohisa Wada , Hirotada Kuriyama
发明人： Tomohisa Wada , Hirotada Kuriyama
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/11 , H01L27/12 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/84 , H01L27/1104 , H01L27/1203 , Y10S257/903
摘要： NMOS transistors as well as pMOS transistors are formed in an SOI layer. One of the impurity diffusion regions of the transistors are respectively connected. A longitudinal end of polysilicon layer extends in one direction to be connected to one of the impurity diffusion regions of transistor. A longitudinal end of a polysilicon layer extends in a direction which is opposite from the above mentioned one direction to be connected to one of the impurity diffusion regions of transistor. As a result, the area for a memory cell region in a static semiconductor memory device can be reduced, and the interconnection structure can be simplified.
摘要翻译： NMOS晶体管以及pMOS晶体管形成在SOI层中。分别连接晶体管的杂质扩散区域之一。多晶硅层的纵向端部在一个方向上延伸以连接到晶体管的一个杂质扩散区域。多晶硅层的纵向端部沿与上述一个方向相反的方向延伸，以连接到晶体管的一个杂质扩散区域。结果，可以减少静态半导体存储器件中的存储单元区域的面积，并且可以简化互连结构。

2. 发明授权

US4811155A Protection circuit for a semiconductor integrated circuit having bipolar transistors 失效
标题翻译：具有双极晶体管的半导体集成电路的保护电路
公开(公告)号：US4811155A
公开(公告)日：1989-03-07
申请号：US142558
申请日：1988-01-11
申请人： Hirotada Kuriyama , Tomohisa Wada , Shuuji Murakami
发明人： Hirotada Kuriyama , Tomohisa Wada , Shuuji Murakami
IPC分类号： H01L27/06 , H01L21/331 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/04 , H01L27/092 , H01L29/73 , H01L29/732 , H01L29/78 , H03K17/0812
CPC分类号： H01L27/0259 , H03K17/08122
摘要： Two resistors are connected in series between an input bonding electrode and an internal circuit, and respective conducting terminals of a first bipolar transistor are connected between the two resistors and a GND bonding electrode which is connected to the internal circuit. Respective conducting terminals of a second bipolar transistor are connected between the two resistors and a V.sub.DD bonding electrode which is connected to the internal circuit. Control terminals of the respective ones of the first and second bipolar transistors are connected to the GND bonding electrode respectively.
摘要翻译：两个电阻器串联连接在输入接合电极和内部电路之间，并且第一双极晶体管的各个导电端子连接在两个电阻器和连接到内部电路的GND接合电极之间。第二双极晶体管的导电端子连接在两个电阻器和连接到内部电路的VDD接合电极之间。第一和第二双极晶体管的各自的控制端子分别连接到GND接合电极。

3. 发明申请

US20050167673A1 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20050167673A1
公开(公告)日：2005-08-04
申请号：US11078581
申请日：2005-03-14
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L21/265 , H01L21/336 , H01L27/11 , H01L27/12 , H01L29/417 , H01L29/45 , H01L29/786 , H01L29/04
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

4. 发明授权

US06441448B1 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US06441448B1
公开(公告)日：2002-08-27
申请号：US09289719
申请日：1999-04-12
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama
IPC分类号： H01L2976
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/1203
摘要： A memory cell which is capable of reducing the memory cell size in SRAM using a field-shield isolation on an SOI substrate. An isolation oxide film is provided between a field-shield isolation plate for n-type transistors and a field-shield isolation plate for p-type transistors.
摘要翻译：一种存储单元，其能够使用SOI衬底上的场屏蔽隔离来降低SRAM中的存储单元尺寸。在n型晶体管的屏蔽隔离板和p型晶体管的场屏蔽隔离板之间设置隔离氧化膜。

5. 发明授权

US06383860B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06383860B2
公开(公告)日：2002-05-07
申请号：US09908607
申请日：2001-07-20
申请人： Shigenobu Maeda , Yasuo Inoue , Hirotada Kuriyama , Shigeto Maegawa , Kyozo Kanamoto , Toshiaki Iwamatsu
发明人： Shigenobu Maeda , Yasuo Inoue , Hirotada Kuriyama , Shigeto Maegawa , Kyozo Kanamoto , Toshiaki Iwamatsu
IPC分类号： H01L218242
CPC分类号： H01L27/10823 , H01L21/84 , H01L27/0688 , H01L27/10841 , H01L27/1203 , H01L29/78642
摘要： A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.
摘要翻译：第一杂质扩散层形成源极/漏极区之一并且还形成位线。形成源极/漏极区域中的另一个并且还形成存储节点的第一半导体层，沟道半导体层和第二半导体层设置在第一杂质扩散层上。电容绝缘膜设置在第二导电层上。电池板设置在存储节点上，其间具有电容器绝缘膜。位线的电容减小，并且由此构成的动态随机存取存储器执行高速操作。

6. 发明授权

US5981990A Semiconductor memory device, method of manufacturing the same and method of using the same 失效
标题翻译：半导体存储器件及其制造方法及其使用方法
公开(公告)号：US5981990A
公开(公告)日：1999-11-09
申请号：US607046
申请日：1996-02-26
申请人： Shigenobu Maeda , Shigeto Maegawa , Hirotada Kuriyama
发明人： Shigenobu Maeda , Shigeto Maegawa , Hirotada Kuriyama
IPC分类号： H01L27/10 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L27/108
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： In a memory cell of an SRAM, a load transistor has a pair of source/drain regions formed to define a channel region, and a gate electrode layer being opposite to the channel region with an insulating layer therebetween. A VVP layer is formed to sandwich the channel region with the gate electrode layer to be opposite to channel region with an insulating layer therebetween. This VVP layer is provided such that GND potential is applied when active and Vcc potential is applied during standby. Thus, a large ON current can be implemented while maintaining a small OFF current of a TFT, even when the power supply voltage is made lower due to reduction in voltage.
摘要翻译：在SRAM的存储单元中，负载晶体管具有形成为限定沟道区的一对源极/漏极区，以及与沟道区相对的栅极电极层，其间具有绝缘层。形成VVP层，以使沟道区域与栅极电极层夹在与沟道区相对的位置，其间具有绝缘层。提供这个VVP层，使得在待机期间施加有源和Vcc电位时施加GND电位。因此，即使当由于电压降低使电源电压降低时，也可以在保持TFT的小的截止电流的同时实现大的导通电流。

7. 发明授权

US5859444A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5859444A
公开(公告)日：1999-01-12
申请号：US795207
申请日：1997-02-05
申请人： Teruhiko Okada , Hirotada Kuriyama , Yoshio Kohno
发明人： Teruhiko Okada , Hirotada Kuriyama , Yoshio Kohno
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L29/76 , H01L27/01 , H01L31/036 , H01L31/112
CPC分类号： H01L29/66765 , H01L27/11 , H01L27/1108 , H01L29/78636
摘要： A semiconductor device is an SRAM cell having a pair of access transistors, a pair of driver transistors and a pair of load transistors. A gate electrode of the load transistor is electrically connected to a region of a semiconductor substrate which is surrounded by a gate electrode of the driver transistor, a channel region of the load transistor is formed opposite to the gate electrode of the load transistor with an insulating film therebetween, and a pair of source/drain regions of the load transistor are formed to sandwich the channel region.
摘要翻译：半导体器件是具有一对存取晶体管，一对驱动晶体管和一对负载晶体管的SRAM单元。负载晶体管的栅电极与由驱动晶体管的栅电极围绕的半导体基板的区域电连接，负载晶体管的沟道区域与负载晶体管的栅电极相对，绝缘并且形成负载晶体管的一对源极/漏极区以夹持沟道区域。

8. 发明授权

US5673230A Semiconductor memory device capable of operating at high speed and stably even under low power supply voltage 失效
标题翻译：半导体存储器件即使在低电源电压下也能够高速且稳定地工作
公开(公告)号：US5673230A
公开(公告)日：1997-09-30
申请号：US602666
申请日：1996-02-16
申请人： Hirotada Kuriyama
发明人： Hirotada Kuriyama
IPC分类号： G11C11/41 , G11C11/412 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419 , G11C11/412
摘要： A memory cell includes a read/write word line R/WL1 driving access transistor Q1 in read and write operations and a write word line WL1 driving access transistor Q2 in the write operation. In the write operation, both access transistors Q1 and Q2 are driven, and storage information is written in the memory cell by a bit line and a /bit line having potentials complementary to each other. On the other hand, in the read operation, only access transistor Q1 is rendered conductive, and storage information is read out through the bit line. Since access transistor Q2 is rendered non-conductive, a P type TFT transistor and an N type transistor operate as a CMOS type inverter having a large voltage gain. Therefore, a sufficient operating margin is secured even in the read operation.
摘要翻译：存储单元包括在读取和写入操作中驱动存取晶体管Q1的读/写字线R / WL1和在写操作中驱动存取晶体管Q2的写字线WL1。在写入操作中，两个存取晶体管Q1和Q2被驱动，并且存储信息通过具有互补电位的位线和/位线写入存储单元。另一方面，在读取操作中，只有存取晶体管Q1导通，并且通过位线读出存储信息。由于存取晶体管Q2不导通，所以P型TFT晶体管和N型晶体管作为具有大电压增益的CMOS型反相器工作。因此，即使在读取操作中也能确保足够的操作余量。

9. 发明授权

US07321152B2 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07321152B2
公开(公告)日：2008-01-22
申请号：US11498800
申请日：2006-08-04
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same.A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

10. 发明授权

US06501178B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06501178B1
公开(公告)日：2002-12-31
申请号：US08795176
申请日：1997-02-04
申请人： Hirotada Kuriyama , Kazuhito Tsutsumi
发明人： Hirotada Kuriyama , Kazuhito Tsutsumi
IPC分类号： H01L2348
CPC分类号： H01L27/11 , H01L23/5226 , H01L27/1108 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： In a semiconductor device, a first conductive layer (2) is located on a semiconductor substrate (14) through an insulating film (13a) and beneath a first insulating layer (13f). On the first insulating layer (13f) is formed a second conductive layer (8) followed by a second insulating layer (13g), either or both of which are very thin. A third conductive layer (6) is placed on the second insulating layer (13g). A connecting column (16) extends from the third conducting layer (6) through and forming an end contact with the second conductive layer (8) to the first conducting layer (2) and the substrate (14), with a greater portion of the column resting upon the substrate (14). The third conductive layer (6) forms the gate electrode (6b) of a top gate type TFT.
摘要翻译：在半导体器件中，第一导电层（2）通过绝缘膜（13a）位于半导体衬底（14）上并位于第一绝缘层（13f）下方。在第一绝缘层（13f）上形成第二导电层（8），随后是第二绝缘层（13g），其中一个或两者都非常薄。第三导电层（6）放置在第二绝缘层（13g）上。连接柱（16）从第三导电层（6）延伸穿过并与第二导电层（8）形成与第一导电层（2）和基板（14）的端部接触，其中较大部分的柱放置在基底（14）上。第三导电层（6）形成顶栅型TFT的栅电极（6b）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式