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1. 发明申请

US20050167673A1 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20050167673A1
公开(公告)日：2005-08-04
申请号：US11078581
申请日：2005-03-14
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L21/265 , H01L21/336 , H01L27/11 , H01L27/12 , H01L29/417 , H01L29/45 , H01L29/786 , H01L29/04
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

2. 发明授权

US07321152B2 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07321152B2
公开(公告)日：2008-01-22
申请号：US11498800
申请日：2006-08-04
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same.A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

3. 发明授权

US06501178B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06501178B1
公开(公告)日：2002-12-31
申请号：US08795176
申请日：1997-02-04
申请人： Hirotada Kuriyama , Kazuhito Tsutsumi
发明人： Hirotada Kuriyama , Kazuhito Tsutsumi
IPC分类号： H01L2348
CPC分类号： H01L27/11 , H01L23/5226 , H01L27/1108 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： In a semiconductor device, a first conductive layer (2) is located on a semiconductor substrate (14) through an insulating film (13a) and beneath a first insulating layer (13f). On the first insulating layer (13f) is formed a second conductive layer (8) followed by a second insulating layer (13g), either or both of which are very thin. A third conductive layer (6) is placed on the second insulating layer (13g). A connecting column (16) extends from the third conducting layer (6) through and forming an end contact with the second conductive layer (8) to the first conducting layer (2) and the substrate (14), with a greater portion of the column resting upon the substrate (14). The third conductive layer (6) forms the gate electrode (6b) of a top gate type TFT.
摘要翻译：在半导体器件中，第一导电层（2）通过绝缘膜（13a）位于半导体衬底（14）上并位于第一绝缘层（13f）下方。在第一绝缘层（13f）上形成第二导电层（8），随后是第二绝缘层（13g），其中一个或两者都非常薄。第三导电层（6）放置在第二绝缘层（13g）上。连接柱（16）从第三导电层（6）延伸穿过并与第二导电层（8）形成与第一导电层（2）和基板（14）的端部接触，其中较大部分的柱放置在基底（14）上。第三导电层（6）形成顶栅型TFT的栅电极（6b）。

4. 发明授权

US06255719B1 Semiconductor device including thermal neutron absorption material 失效
标题翻译：包括热中子吸收材料的半导体器件
公开(公告)号：US06255719B1
公开(公告)日：2001-07-03
申请号：US09201833
申请日：1998-12-01
申请人： Hirotada Kuriyama , Kazuhito Tsutsumi , Yutaka Arita , Tatsuhiko Akiyama , Tadafumi Kishimoto
发明人： Hirotada Kuriyama , Kazuhito Tsutsumi , Yutaka Arita , Tatsuhiko Akiyama , Tadafumi Kishimoto
IPC分类号： H01L23552
CPC分类号： H01L23/556 , H01L23/552 , H01L2924/0002 , H01L2924/1627 , Y10S257/913 , H01L2924/00
摘要： A boron nitride inclusion sheet is applied on the surface of a mold package enclosing a semiconductor chip so as to prevent soft error caused by a thermal neutron.
摘要翻译：在封装半导体芯片的模具封装的表面上施加氮化硼夹层板，以防止由热中子引起的软误差。

5. 发明申请

US20060267012A1 Thin-film transistor and method of fabricating the same 失效
公开(公告)号：US20060267012A1
公开(公告)日：2006-11-30
申请号：US11498800
申请日：2006-08-04
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L31/00
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

6. 发明授权

US07187040B2 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07187040B2
公开(公告)日：2007-03-06
申请号：US11078581
申请日：2005-03-14
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

7. 发明授权

US07112854B1 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07112854B1
公开(公告)日：2006-09-26
申请号：US08850631
申请日：1997-05-02
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L29/78
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

8. 发明授权

US06441448B1 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US06441448B1
公开(公告)日：2002-08-27
申请号：US09289719
申请日：1999-04-12
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama
IPC分类号： H01L2976
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/1203
摘要： A memory cell which is capable of reducing the memory cell size in SRAM using a field-shield isolation on an SOI substrate. An isolation oxide film is provided between a field-shield isolation plate for n-type transistors and a field-shield isolation plate for p-type transistors.
摘要翻译：一种存储单元，其能够使用SOI衬底上的场屏蔽隔离来降低SRAM中的存储单元尺寸。在n型晶体管的屏蔽隔离板和p型晶体管的场屏蔽隔离板之间设置隔离氧化膜。

9. 发明授权

US06383860B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06383860B2
公开(公告)日：2002-05-07
申请号：US09908607
申请日：2001-07-20
申请人： Shigenobu Maeda , Yasuo Inoue , Hirotada Kuriyama , Shigeto Maegawa , Kyozo Kanamoto , Toshiaki Iwamatsu
发明人： Shigenobu Maeda , Yasuo Inoue , Hirotada Kuriyama , Shigeto Maegawa , Kyozo Kanamoto , Toshiaki Iwamatsu
IPC分类号： H01L218242
CPC分类号： H01L27/10823 , H01L21/84 , H01L27/0688 , H01L27/10841 , H01L27/1203 , H01L29/78642
摘要： A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.
摘要翻译：第一杂质扩散层形成源极/漏极区之一并且还形成位线。形成源极/漏极区域中的另一个并且还形成存储节点的第一半导体层，沟道半导体层和第二半导体层设置在第一杂质扩散层上。电容绝缘膜设置在第二导电层上。电池板设置在存储节点上，其间具有电容器绝缘膜。位线的电容减小，并且由此构成的动态随机存取存储器执行高速操作。

10. 发明授权

US5981990A Semiconductor memory device, method of manufacturing the same and method of using the same 失效
标题翻译：半导体存储器件及其制造方法及其使用方法
公开(公告)号：US5981990A
公开(公告)日：1999-11-09
申请号：US607046
申请日：1996-02-26
申请人： Shigenobu Maeda , Shigeto Maegawa , Hirotada Kuriyama
发明人： Shigenobu Maeda , Shigeto Maegawa , Hirotada Kuriyama
IPC分类号： H01L27/10 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L27/108
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： In a memory cell of an SRAM, a load transistor has a pair of source/drain regions formed to define a channel region, and a gate electrode layer being opposite to the channel region with an insulating layer therebetween. A VVP layer is formed to sandwich the channel region with the gate electrode layer to be opposite to channel region with an insulating layer therebetween. This VVP layer is provided such that GND potential is applied when active and Vcc potential is applied during standby. Thus, a large ON current can be implemented while maintaining a small OFF current of a TFT, even when the power supply voltage is made lower due to reduction in voltage.
摘要翻译：在SRAM的存储单元中，负载晶体管具有形成为限定沟道区的一对源极/漏极区，以及与沟道区相对的栅极电极层，其间具有绝缘层。形成VVP层，以使沟道区域与栅极电极层夹在与沟道区相对的位置，其间具有绝缘层。提供这个VVP层，使得在待机期间施加有源和Vcc电位时施加GND电位。因此，即使当由于电压降低使电源电压降低时，也可以在保持TFT的小的截止电流的同时实现大的导通电流。

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