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1. 发明授权

US5994735A Semiconductor device having a vertical surround gate metal-oxide semiconductor field effect transistor, and manufacturing method thereof 失效
标题翻译：具有垂直环绕栅极金属氧化物半导体场效应晶体管的半导体器件及其制造方法
公开(公告)号：US5994735A
公开(公告)日：1999-11-30
申请号：US582810
申请日：1996-01-04
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L27/11 , H01L27/12 , H01L29/78 , H01L29/76 , H01L27/01 , H01L29/94
CPC分类号： H01L27/092 , H01L27/10823 , H01L27/10841 , H01L27/1104 , H01L27/1203 , H01L29/66666 , H01L29/7827
摘要： A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.
摘要翻译：可以获得占据小面积的场效应晶体管和使用其的半导体器件。栅电极设置在基板上，源极区域之间插入有第一层间绝缘膜。栅电极被第二层间绝缘膜覆盖。提供用于暴露源区域的一部分表面的接触孔，以穿透第一层间绝缘膜，栅电极和第二层间绝缘膜。接触孔的侧壁表面被栅极绝缘膜覆盖。第一导电类型的第一半导体层设置在与其接触的源极区域的表面上，直到栅电极的下表面。沟道半导体层设置在第一半导体层的表面上直到栅电极的上表面。在沟道半导体层上设置有用作漏极区的第一导电类型的第二半导体层。

2. 发明授权

US06441448B1 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US06441448B1
公开(公告)日：2002-08-27
申请号：US09289719
申请日：1999-04-12
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama
IPC分类号： H01L2976
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/1203
摘要： A memory cell which is capable of reducing the memory cell size in SRAM using a field-shield isolation on an SOI substrate. An isolation oxide film is provided between a field-shield isolation plate for n-type transistors and a field-shield isolation plate for p-type transistors.
摘要翻译：一种存储单元，其能够使用SOI衬底上的场屏蔽隔离来降低SRAM中的存储单元尺寸。在n型晶体管的屏蔽隔离板和p型晶体管的场屏蔽隔离板之间设置隔离氧化膜。

3. 发明授权

US06420751B1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06420751B1
公开(公告)日：2002-07-16
申请号：US09640880
申请日：2000-08-18
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
IPC分类号： H01L2976
CPC分类号： H01L27/092 , H01L27/10823 , H01L27/10841 , H01L27/1104 , H01L27/1203 , H01L29/66666 , H01L29/7827
摘要： A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.
摘要翻译：可以获得占据小面积的场效应晶体管和使用其的半导体器件。栅电极设置在基板上，源极区域之间插入有第一层间绝缘膜。栅电极被第二层间绝缘膜覆盖。提供用于暴露源区域的一部分表面的接触孔，以穿透第一层间绝缘膜，栅电极和第二层间绝缘膜。接触孔的侧壁表面被栅极绝缘膜覆盖。第一导电类型的第一半导体层设置在与其接触的源极区域的表面上，直到栅电极的下表面。沟道半导体层设置在第一半导体层的表面上直到栅电极的上表面。在沟道半导体层上设置有用作漏极区的第一导电类型的第二半导体层。

4. 发明授权

US6127209A Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US6127209A
公开(公告)日：2000-10-03
申请号：US295363
申请日：1999-04-21
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L27/11 , H01L27/12 , H01L29/78 , H01L21/00 , H01L21/8232
CPC分类号： H01L27/092 , H01L27/10823 , H01L27/10841 , H01L27/1104 , H01L27/1203 , H01L29/66666 , H01L29/7827
摘要： A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.

5. 发明授权

US06882006B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06882006B2
公开(公告)日：2005-04-19
申请号：US10188103
申请日：2002-07-03
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L27/11 , H01L27/12 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/092 , H01L27/10823 , H01L27/10841 , H01L27/1104 , H01L27/1203 , H01L29/66666 , H01L29/7827
摘要： A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.
摘要翻译：可以获得占据小面积的场效应晶体管和使用其的半导体器件。栅电极设置在基板上，源极区域之间插入有第一层间绝缘膜。栅电极被第二层间绝缘膜覆盖。提供用于暴露源区域的一部分表面的接触孔，以穿透第一层间绝缘膜，栅电极和第二层间绝缘膜。接触孔的侧壁表面被栅极绝缘膜覆盖。第一导电类型的第一半导体层设置在与其接触的源极区域的表面上，直到栅电极的下表面。沟道半导体层设置在第一半导体层的表面上直到栅电极的上表面。在沟道半导体层上设置有用作漏极区的第一导电类型的第二半导体层。

6. 发明授权

US07321152B2 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07321152B2
公开(公告)日：2008-01-22
申请号：US11498800
申请日：2006-08-04
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same.A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

7. 发明申请

US20050167673A1 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20050167673A1
公开(公告)日：2005-08-04
申请号：US11078581
申请日：2005-03-14
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L21/265 , H01L21/336 , H01L27/11 , H01L27/12 , H01L29/417 , H01L29/45 , H01L29/786 , H01L29/04
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

8. 发明授权

US06383860B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06383860B2
公开(公告)日：2002-05-07
申请号：US09908607
申请日：2001-07-20
申请人： Shigenobu Maeda , Yasuo Inoue , Hirotada Kuriyama , Shigeto Maegawa , Kyozo Kanamoto , Toshiaki Iwamatsu
发明人： Shigenobu Maeda , Yasuo Inoue , Hirotada Kuriyama , Shigeto Maegawa , Kyozo Kanamoto , Toshiaki Iwamatsu
IPC分类号： H01L218242
CPC分类号： H01L27/10823 , H01L21/84 , H01L27/0688 , H01L27/10841 , H01L27/1203 , H01L29/78642
摘要： A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.
摘要翻译：第一杂质扩散层形成源极/漏极区之一并且还形成位线。形成源极/漏极区域中的另一个并且还形成存储节点的第一半导体层，沟道半导体层和第二半导体层设置在第一杂质扩散层上。电容绝缘膜设置在第二导电层上。电池板设置在存储节点上，其间具有电容器绝缘膜。位线的电容减小，并且由此构成的动态随机存取存储器执行高速操作。

9. 发明授权

US5981990A Semiconductor memory device, method of manufacturing the same and method of using the same 失效
标题翻译：半导体存储器件及其制造方法及其使用方法
公开(公告)号：US5981990A
公开(公告)日：1999-11-09
申请号：US607046
申请日：1996-02-26
申请人： Shigenobu Maeda , Shigeto Maegawa , Hirotada Kuriyama
发明人： Shigenobu Maeda , Shigeto Maegawa , Hirotada Kuriyama
IPC分类号： H01L27/10 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L27/108
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： In a memory cell of an SRAM, a load transistor has a pair of source/drain regions formed to define a channel region, and a gate electrode layer being opposite to the channel region with an insulating layer therebetween. A VVP layer is formed to sandwich the channel region with the gate electrode layer to be opposite to channel region with an insulating layer therebetween. This VVP layer is provided such that GND potential is applied when active and Vcc potential is applied during standby. Thus, a large ON current can be implemented while maintaining a small OFF current of a TFT, even when the power supply voltage is made lower due to reduction in voltage.
摘要翻译：在SRAM的存储单元中，负载晶体管具有形成为限定沟道区的一对源极/漏极区，以及与沟道区相对的栅极电极层，其间具有绝缘层。形成VVP层，以使沟道区域与栅极电极层夹在与沟道区相对的位置，其间具有绝缘层。提供这个VVP层，使得在待机期间施加有源和Vcc电位时施加GND电位。因此，即使当由于电压降低使电源电压降低时，也可以在保持TFT的小的截止电流的同时实现大的导通电流。

10. 发明授权

US5517038A Semiconductor device including three-dimensionally disposed logic elements for improving degree of integration 失效
标题翻译：半导体器件包括用于提高集成度的三维布置的逻辑元件
公开(公告)号：US5517038A
公开(公告)日：1996-05-14
申请号：US348211
申请日：1994-11-28
申请人： Shigenobu Maeda , Hirotada Kuriyama
发明人： Shigenobu Maeda , Hirotada Kuriyama
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , H01L27/108
CPC分类号： H01L27/1108 , G11C11/412 , G11C11/418 , G11C11/419 , Y10S257/903 , Y10S257/904
摘要： Adjacent memory cells has a two-layer structure formed of first layer and second layer. The first layer is provided with driver transistors of the memory cell, access transistors of the memory cell, and driver transistors formed of the memory cell. The second layer is provided with load transistors of the memory cell, load transistors and of the memory cell, and access transistors of the memory cell. The transistors formed in the first layer are of an NMOS type, and the transistors formed in the second layer are of a PMOS type.
摘要翻译：相邻的存储单元具有由第一层和第二层形成的双层结构。第一层设置有存储单元的驱动器晶体管，存储单元的存取晶体管和由存储单元形成的驱动晶体管。第二层设置有存储单元，负载晶体管和存储单元的负载晶体管，以及存储单元的存取晶体管。形成在第一层中的晶体管是NMOS型，并且在第二层中形成的晶体管是PMOS型的。

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