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1. 发明授权

US06363010B1 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06363010B1
公开(公告)日：2002-03-26
申请号：US09899290
申请日：2001-07-06
申请人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
发明人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
IPC分类号： G11C1604
摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is “m”. Specifically, when the number is determined such that 22=4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

2. 发明授权

US06545909B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06545909B2
公开(公告)日：2003-04-08
申请号：US10094215
申请日：2002-03-11
申请人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
发明人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C7/1006 , G11C7/1078 , G11C7/12 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A memory cell array in which memory cells storable multilevel data are arranged in a matrix. Bit line controllers have latch circuits configured to latch write data and sense circuits configured to sense read data. Bit lines connect the bit line controllers and the memory cells. The bit lines supply write data from the latch circuits to the memory cells during data write mode and supply read data from the memory cells to the sense circuits during data read mode. The number of the multilevel data is 4 and the number of the sense circuits is 2, or the number of the multilevel data is 8 and the number of the sense circuits is 3.
摘要翻译：存储单元阵列，其中存储单元可存储多级数据以矩阵形式排列。位线控制器具有被配置为锁存写入数据和被配置为感测读取数据的感测电路的锁存电路。位线连接位线控制器和存储单元。在数据写入模式期间，位线将写入数据从锁存电路提供给存储器单元，并且在数据读取模式期间将读取数据从存储器单元提供给读出电路。多级数据的数量为4，感测电路的数量为2，多级数据的数量为8，感测电路的数量为3。

3. 发明授权

US6044013A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US6044013A
公开(公告)日：2000-03-28
申请号：US314446
申请日：1999-05-19
申请人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
发明人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
IPC分类号： G11C7/10 , G11C7/12 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/24 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C7/1006 , G11C7/1078 , G11C7/12 , G11C2211/5621 , G11C2211/5642
摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2.sup.m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is "m". Specifically, when the number is determined such that 2.sup.2 =4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.
摘要翻译：提供了用于将数据输入/输出线和一个位线BL彼此连接的位线控制器。位线控制器具有用于将从数据输入/输出线提供的多电平写入数据锁存到存储单元的数据锁存器和用于感测和锁存从存储单元晶体管输出到一个位线BL的数据的读出放大器。当要输出到一个位线BL的多电平数据的数量为2m（m是不小于2的自然数）= n电平时，每个数据锁存器和读出放大器的数量为“m”。具体地说，当确定数字使得22 = 4时，每个数据锁存器和读出放大器的数量是两个。结果，提供了一种能够减小列系统电路的尺寸并实现高度集成的结构的非易失性半导体存储器件。

4. 发明授权

US5969985A Nonvolatile semiconductor memory device 失效
公开(公告)号：US5969985A
公开(公告)日：1999-10-19
申请号：US816830
申请日：1997-03-18
申请人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
发明人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
IPC分类号： G11C7/10 , G11C7/12 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/24 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C7/1006 , G11C7/1078 , G11C7/12 , G11C2211/5621 , G11C2211/5642
摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2.sup.m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is "m". Specifically, when the number is determined such that 2.sup.2 =4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

5. 发明授权

US06282117B1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06282117B1
公开(公告)日：2001-08-28
申请号：US09532329
申请日：2000-03-21
申请人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
发明人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C7/1006 , G11C7/1078 , G11C7/12 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When, the number of multilevel data to be output to one bit line BL is 2m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is “m”. Specifically, when the number is determined such that 22=4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.
摘要翻译：提供了用于将数据输入/输出线和一个位线BL彼此连接的位线控制器。位线控制器具有用于将从数据输入/输出线提供的多电平写入数据锁存到存储单元的数据锁存器和用于感测和锁存从存储单元晶体管输出到一个位线BL的数据的读出放大器。当要输出到一个位线BL的多电平数据的数量为2m（m是不小于2的自然数）= n电平时，每个数据锁存器和读出放大器的数量为“m”。具体地说，当确定数字使得22 = 4时，每个数据锁存器和读出放大器的数量是两个。结果，提供了一种能够减小列系统电路的尺寸并实现高度集成的结构的非易失性半导体存储器件。

6. 发明授权

US5933436A Error correction/detection circuit and semiconductor memory device using the same 失效
标题翻译：误差校正/检测电路及使用其的半导体存储器件
公开(公告)号：US5933436A
公开(公告)日：1999-08-03
申请号：US611818
申请日：1996-03-06
申请人： Toru Tanzawa , Tomoharu Tanaka , Riichiro Shirota , Kazunori Ohuchi
发明人： Toru Tanzawa , Tomoharu Tanaka , Riichiro Shirota , Kazunori Ohuchi
IPC分类号： G06F12/16 , G06F11/10 , H03M13/15 , G11C29/00
CPC分类号： G06F11/1008 , H03M13/151
摘要： An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size calculating circuit for calculating a position and a size of an error from said syndrome; and an error correction circuit for correcting an error for at least information data input in a second cycle on a basis of the position and the size of the error obtained in said error position/size calculating circuit and for outputting at least error-corrected information data.
摘要翻译：一种纠错/检测电路，包括：从第一周期输入的信息数据和检查数据产生校正子的校正子产生电路; 以及误差位置/尺寸计算电路，用于计算所述综合征的误差的位置和尺寸; 以及误差校正电路，用于根据在所述误差位置/尺寸计算电路中获得的误差的位置和尺寸，校正至少在第二周期中输入的信息数据的误差，并且至少输出错误校正的信息数据。

7. 发明授权

US5602789A Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller 失效
标题翻译：具有写入验证控制器的电可擦除和可编程的非易失性和多级存储器系统
公开(公告)号：US5602789A
公开(公告)日：1997-02-11
申请号：US518024
申请日：1995-08-22
申请人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
IPC分类号： G11C11/56 , G11C16/34 , G11C29/50 , G01R31/28
CPC分类号： G11C16/3418 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/3404 , G11C16/3413 , G11C16/3431 , G11C16/3459 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/0403 , G11C2211/5621
摘要： An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.
摘要翻译：用于存储多级数据的EEPROM包括存储单元阵列，其中电可擦除可编程存储器单元被排列成矩阵，并且每个存储单元具有至少三个存储状态，第一存储单元写入数据的写入电路以及分别由读出放大器，数据锁存电路和检测电路构成的第二写入验证装置，用于分别验证存储器单元的写入不足状态和存储单元的过量写入状态，附加写入电路在写入状态不足的情况下向存储器单元写入数据，以及附加擦除电路，用于在超量写入状态下从存储单元附加擦除数据。

8. 发明授权

US5386422A Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels 失效
公开(公告)号：US5386422A
公开(公告)日：1995-01-31
申请号：US229761
申请日：1994-04-19
申请人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
IPC分类号： G11C11/56 , G11C16/34 , G11C29/50 , G01R31/28
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/3404 , G11C16/3413 , G11C16/3418 , G11C16/3431 , G11C16/3459 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/0403 , G11C2211/5621
摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

9. 发明授权

US6081454A Electrically erasable programmable read-only memory with threshold value controller for data programming 失效
标题翻译：电可擦除可编程只读存储器，具有用于数据编程的阈值控制器
公开(公告)号：US6081454A
公开(公告)日：2000-06-27
申请号：US145466
申请日：1998-09-02
申请人： Kazunori Ohuchi , Tomoharu Tanaka , Yoshihisa Iwata , Yasuo Itoh , Masaki Momodomi , Fujio Masuoka
发明人： Kazunori Ohuchi , Tomoharu Tanaka , Yoshihisa Iwata , Yasuo Itoh , Masaki Momodomi , Fujio Masuoka
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/00 , G11C29/12 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/06
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3454
摘要： A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific biasing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplying the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.
摘要翻译： NAND单元型电可擦除可编程只读存储器具有包含NAND单元单元的存储器阵列部分。每个NAND单元单元具有作为存储单元晶体管的浮栅型金属氧化物半导体场效应晶体管的串联阵列。存储器部分与控制门控制器，数据锁存电路，读出放大器部分和数据比较器相关联，其经由输出缓冲器连接到验证终止检测器。当在数据编程模式下将数据一次写入所选择的存储单元中时，将特定的偏置电压施加到所选择的单元，从而验证所选存储单元的实际电数据写入状态。如果比较器检测到验证的写入条件不满意，则通过向所选择的单元格额外提供补偿所选择的存储单元晶体管中的验证的写入条件的不满足的适当电压来重复执行数据重写操作。

10. 发明授权

US5523980A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5523980A
公开(公告)日：1996-06-04
申请号：US364990
申请日：1994-12-28
申请人： Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Kazunori Ohuchi , Tetsuo Endoh
发明人： Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Kazunori Ohuchi , Tetsuo Endoh
IPC分类号： G11C16/06 , G11C8/12 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/34 , H01L29/78 , G11C8/00
CPC分类号： G11C8/12 , G11C16/0483
摘要： A NAND-cell type EEPROM having a plurality of bit lines, a plurality of control gate lines intersecting with the bit lines, and a plurality of memory cells driven by applying a potential to the control gate lines for selectively storing data, supplying data to the bit lines and receiving data therefrom. The memory cells form a plurality of cell units. The memory cells constituting each cell unit are connected in series to one bit line by a common selecting gate transistor. A plurality of data latch circuits are provided on the bit lines, respectively, for storing data to be written into the memory cells selected by the control gate lines. Further, a plurality of selecting gate drivers are provided to correspond to the cell units, respectively, for driving the control gate lines. A row decoder decodes row addresses for driving the selecting gate drivers and the control gate lines. A plurality of block-address latch circuits are provided to correspond to the selecting gate drivers, respectively, for temporarily storing signals derived from a row address by the row decoder, thereby to select at least two of the selecting gate drivers at the same time in order to write data.
摘要翻译：具有多个位线的NAND单元型EEPROM，与位线相交的多个控制栅极线，以及通过向控制栅极线施加电位而驱动的多个存储单元，用于选择性地存储数据，向位线和从其接收数据。存储单元形成多个单元单元。构成每个单元单元的存储单元通过公共选择栅极晶体管串联连接到一个位线。分别在位线上提供多个数据锁存电路，用于存储要写入由控制栅极线选择的存储单元的数据。此外，分别提供多个选择栅极驱动器以对应于用于驱动控制栅极线的单元单元。行解码器解码用于驱动选择栅极驱动器和控制栅极线的行地址。提供多个块地址锁存电路以分别对应于选择栅极驱动器，用于临时存储由行解码器从行地址导出的信号，从而同时选择至少两个选择栅极驱动器命令写数据。

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