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1. 发明授权

US5556797A Method of fabricating a self-aligned double recess gate profile 失效
标题翻译：制造自对准双凹槽浇口型材的方法
公开(公告)号：US5556797A
公开(公告)日：1996-09-17
申请号：US453676
申请日：1995-05-30
申请人： Tom Y. Chi , Liping D. Hou , Kusol Lee , Danny Li , Ishver K. Naik , Tom Quach
发明人： Tom Y. Chi , Liping D. Hou , Kusol Lee , Danny Li , Ishver K. Naik , Tom Quach
IPC分类号： H01L21/338 , H01L29/812 , H01L21/8258
CPC分类号： H01L29/66871 , H01L29/8128
摘要： A method of fabricating a self-aligned double gate recess profile in a semiconductor substrate is disclosed in which a first mask layer is formed over the substrate. A second mask layer having an opening is formed over the first mask layer. An opening at least as wide as the second mask layer's opening is formed through the first mask layer to expose the substrate beneath the second mask layer's opening. A first recess is etched in the semiconductor through the second mask layer's opening. The first mask layer's opening is then uniformly expanded and a wider recess, aligned to the first recess, is then formed in the semiconductor. The method is particularly applicable to the formation of self-aligned gate and channel recesses in a GaAs MESFET.
摘要翻译：公开了一种在半导体衬底中制造自对准双栅凹槽轮廓的方法，其中在衬底上形成第一掩模层。在第一掩模层上形成具有开口的第二掩模层。通过第一掩模层形成至少与第二掩模层开口一样宽的开口，以将第二掩模层开口下方的基板曝光。通过第二掩模层的开口在半导体中蚀刻第一凹槽。然后将第一掩模层的开口均匀地膨胀，然后在半导体中形成与第一凹部对准的更宽的凹部。该方法特别适用于GaAs MESFET中自对准栅极和沟槽的形成。

2. 发明授权

US5705432A Process for providing clean lift-off of sputtered thin film layers 失效
标题翻译：提供溅射薄膜层清洁剥离的工艺
公开(公告)号：US5705432A
公开(公告)日：1998-01-06
申请号：US566197
申请日：1995-12-01
申请人： Kusol Lee , Tom Quach , Danny Li , Liping D. Hou , Sam Chung , Tom Y. Chi
发明人： Kusol Lee , Tom Quach , Danny Li , Liping D. Hou , Sam Chung , Tom Y. Chi
IPC分类号： H01L21/027 , H01L21/465
CPC分类号： H01L21/0272 , Y10S438/951
摘要： A unique photoresist process is provided which achieves clean and complete lift-off of a thin film layer such as a sputtered thin film formed on a photoresist which is formed above a semiconductor substrate. The process of the present invention relies on a reentrant photoresist profile which breaks the continuity of the thin film layer. Accordingly, the process of the present invention ensures a clean lift-off. The desired photoresist profile which breaks the continuity of the thin film layer can be obtained by a typical photoresist process preceded by an oxidation process that takes place on the surface of the semiconductor substrate. The oxidation process provides a thin native oxide layer with thickness ranging from about 30 to 50 .ANG.. No extra processing steps involving dielectric film deposition and etch are required to achieve clean lift-off. Nevertheless, the process of the present invention ensures the clean lift-off of the thin film layer. Accordingly, the process of the present invention provides good visual and electrical yields.
摘要翻译：提供了一种独特的光刻胶工艺，其实现了清洁和完全剥离薄膜层，例如形成在半导体衬底上的光致抗蚀剂上形成的溅射薄膜。本发明的方法依赖于破坏薄膜层的连续性的可重入光致抗蚀剂轮廓。因此，本发明的方法确保了清洁的剥离。可以通过在半导体衬底的表面上发生的氧化工艺之前的典型的光致抗蚀剂工艺来获得破坏薄膜层的连续性的期望的光致抗蚀剂轮廓。氧化过程提供厚度范围为约30至50安培的薄的天然氧化物层。不需要涉及介电膜沉积和蚀刻的额外处理步骤来实现干净的剥离。然而，本发明的方法确保了薄膜层的清洁剥离。因此，本发明的方法提供良好的视觉和电产量。

3. 发明授权

US4317700A Method of fabrication of planar bubble domain device structures 失效
标题翻译：平面气泡域装置结构的制造方法
公开(公告)号：US4317700A
公开(公告)日：1982-03-02
申请号：US179843
申请日：1980-08-20
申请人： Kunihide Tanaka , Michael T. Elliott , Sam Chung , James Pau , Linda Gray , Liping D. Hou , Mary F'Mayer , David Warren , Karen Finch
发明人： Kunihide Tanaka , Michael T. Elliott , Sam Chung , James Pau , Linda Gray , Liping D. Hou , Mary F'Mayer , David Warren , Karen Finch
IPC分类号： G11C11/14 , H01F10/06 , H01F41/14 , H01F41/34 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01F41/34 , H01F10/06
摘要： A method of fabricating a bubble domain device composite structure on a substrate of depositing a barrier layer of a suitable polymeric dielectric material on the substrate; subsequently depositing a layer of electrically conductive material thereover; subsequently depositing a spacer layer of a liquid polymeric dielectric material over the conductive layer; processing the spacer layer so that the surface of the spacer layer is substantially planar; and subsequently depositing a layer of a magnetically operative material over the spacer layer.
摘要翻译：一种在衬底上制造气泡区域器件复合结构的方法，该衬底在衬底上沉积合适的聚合物介电材料的阻挡层; 随后在其上沉积一层导电材料; 随后在所述导电层上沉积液体聚合物介电材料的间隔层; 处理间隔层，使得间隔层的表面基本上是平面的; 随后在间隔层上沉积一层磁性操作材料。

4. 发明授权

US5998817A High power prematched MMIC transistor with improved ground potential continuity 失效
标题翻译：具有改进的接地电位连续性的大功率预先配置的MMIC晶体管
公开(公告)号：US5998817A
公开(公告)日：1999-12-07
申请号：US963529
申请日：1997-11-03
申请人： Cheng P. Wen , Peter Chu , Michael R. Cole , Wah S. Wong , Robert F. Wang , Liping D. Hou
发明人： Cheng P. Wen , Peter Chu , Michael R. Cole , Wah S. Wong , Robert F. Wang , Liping D. Hou
IPC分类号： H01L25/18 , H01L23/482 , H01L23/66 , H01L25/04 , H01L29/80
CPC分类号： H01L23/4824 , H01L23/66 , H01L2223/6644 , H01L2924/0002 , H01L2924/3011
摘要： A multicell transistor for use in a circuit has an input ground plane for an input waveguide and an output ground plane for an output waveguide. The multicell transistor includes a gate electrode coupled to the input waveguide, a drain electrode coupled to the output waveguide, and a source electrode coupled to the input ground plane. An output ground strap spaced from the drain electrode couples the output ground plane to the source electrode. A pair of transmission lines are orthogonally connected to and extend from the gate electrode to form a pair of inductors for matching the impedances of the gate electrode and the input waveguide.
摘要翻译：用于电路的多晶体管晶体管具有用于输入波导的输入接地平面和用于输出波导的输出接地平面。多晶体管晶体管包括耦合到输入波导的栅电极，耦合到输出波导的漏电极和耦合到输入接地层的源电极。与漏极间隔开的输出接地带将输出接地平面耦合到源电极。一对传输线与栅电极正交连接并从栅电极延伸，形成一对用于匹配栅电极和输入波导的阻抗的电感器。

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