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1. 发明授权

US06803801B2 CMOS level shifters using native devices 失效
标题翻译：使用本地设备的CMOS电平移位器
公开(公告)号：US06803801B2
公开(公告)日：2004-10-12
申请号：US10289949
申请日：2002-11-07
申请人： Todd Randazzo , Scott Savage , Edson Porter , Matthew Russell , Kenneth Szajda , Hoang Nguyen
发明人： Todd Randazzo , Scott Savage , Edson Porter , Matthew Russell , Kenneth Szajda , Hoang Nguyen
IPC分类号： H03L500
CPC分类号： H03K17/102 , H03K3/356113
摘要： A level shifter circuit configured for use between a core of a chip and input/output transistor of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.
摘要翻译：一种电平移位器电路，被配置为在芯片的核心和芯片的输入/输出晶体管之间使用，以屏蔽驻留在芯上的低电压器件。电平移位器电路包括在其栅极上具有VDDCORE的耐压本机器件，并且每个耐压本机器件与芯上的低电压晶体管级联。

2. 发明申请

US20060103999A1 Use of a known common-mode voltage for input overvoltage protection in pseudo-differential receivers 有权
标题翻译：在伪差分接收机中使用已知的共模电压进行输入过压保护
公开(公告)号：US20060103999A1
公开(公告)日：2006-05-18
申请号：US10988122
申请日：2004-11-12
申请人： Todd Randazzo
发明人： Todd Randazzo
IPC分类号： H02H9/04
CPC分类号： H03F1/52
摘要： A method and apparatus are provided for protecting elements of a receiver from overvoltages in a pseudo-differential signal having a true signal and a reference voltage. The method and apparatus limit the true signal to a protection voltage, which is correlated to the reference voltage, to produce a protected true signal. The protected true signal and the reference voltage are applied to inputs of the receiver.
摘要翻译：提供了一种方法和装置，用于在具有真实信号和参考电压的伪差分信号中保护接收器的元件免受过电压。该方法和装置将真实信号限制为与参考电压相关的保护电压，以产生受保护的真实信号。受保护的真实信号和参考电压被施加到接收器的输入。

3. 发明申请

US20050245226A1 Resistive voltage-down regulator for integrated circuit receivers 有权
标题翻译：用于集成电路接收器的电阻降压稳压器
公开(公告)号：US20050245226A1
公开(公告)日：2005-11-03
申请号：US10835936
申请日：2004-04-30
申请人： Todd Randazzo
发明人： Todd Randazzo
IPC分类号： H03K19/003 , H04B1/28
CPC分类号： H03K19/00384
摘要： A receiver circuit is provided on an integrated circuit. The receiver circuit includes first and second power supply terminals, a ground supply terminal, a resistive element coupled between the first and second power supply terminals, and a receiver biased between the second power supply terminal and the ground supply terminal. The receiver draws a bias current through the resistive element, which varies as a positive function with a voltage on the second power supply terminal. The voltage on the second power supply terminal varies as an inverse function of the bias current.
摘要翻译：在集成电路上提供接收器电路。接收器电路包括第一和第二电源端子，接地电源端子，耦合在第一和第二电源端子之间的电阻元件以及偏置在第二电源端子和地电源端子之间的接收器。接收器通过电阻元件吸收偏置电流，该电阻元件随着第二电源端子上的电压作为正函数而变化。第二电源端子上的电压作为偏置电流的反向函数而变化。

4. 发明申请

US20050042818A1 Analog capacitor in dual damascene process 有权
标题翻译：双镶嵌工艺中的模拟电容器
公开(公告)号：US20050042818A1
公开(公告)日：2005-02-24
申请号：US10959868
申请日：2004-10-06
申请人： Todd Randazzo , Kenneth Fuchs , John de Walker
发明人： Todd Randazzo , Kenneth Fuchs , John de Walker
IPC分类号： H01L23/522 , H01L21/8234
CPC分类号： H01L21/76807 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section. Portions of the upper dielectric layer and the second capacitor electrode section are selectively removed to form a first via cavity that extends through the upper dielectric layer and the edge portion of the second capacitor electrode section. This exposes the edge portion of the second capacitor electrode section within the first via cavity. The first via cavity is filled with a via metal, which makes electrical connection with the edge portion of the second capacitor electrode section that is exposed within the first via cavity.
摘要翻译：一种用于形成电容结构的方法，其包括其中具有第一电容器电极部分的上层。在上层附近形成电容器电介质层。电容器电介质层覆盖第一电容器电极部分。在电容器电介质层附近形成第二电容器电极层。第二电容器电极层包括至少部分地覆盖第一电容器电极部分并且具有延伸超过下面的第一电容器电极部分的边缘部分的第二电容器电极部分。电容器电介质层设置在第一电容电极部分和第二电容器电极部分之间。在第二电容器电极部分附近形成上介电层。选择性地去除上电介质层和第二电容器电极部分的部分以形成延伸穿过上电介质层和第二电容器电极部分的边缘部分的第一通孔。这使第二电容电极部分的边缘部分暴露在第一通孔腔内。第一通孔腔填充有通孔金属，其与第一电容器电极部分的暴露在第一通孔腔内的边缘部分电连接。

5. 发明授权

US08324927B2 High speed multiple memory interface I/O cell 有权
标题翻译：高速多存储器接口I / O单元
公开(公告)号：US08324927B2
公开(公告)日：2012-12-04
申请号：US12970071
申请日：2010-12-16
申请人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
发明人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
IPC分类号： H03K17/16
CPC分类号： G11C29/02 , G11C7/04 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2029/5602 , G11C2207/105 , G11C2207/2254
摘要： An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.
摘要翻译：输入/输出（I / O）单元包括一个或多个可驱动器段和一个或多个片上终端（ODT）能力段。 I / O单元可以被配置为处于第一模式的输出驱动器，并且在第二模式中将Ivenin等效终止。

6. 发明申请

US20110084725A1 HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL 有权
标题翻译：高速多存储器接口I / O单元
公开(公告)号：US20110084725A1
公开(公告)日：2011-04-14
申请号：US12970071
申请日：2010-12-16
申请人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
发明人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
IPC分类号： H03K19/003
CPC分类号： G11C29/02 , G11C7/04 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2029/5602 , G11C2207/105 , G11C2207/2254
摘要： An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.
摘要翻译：输入/输出（I / O）单元包括一个或多个可驱动器段和一个或多个片上终端（ODT）能力段。 I / O单元可以被配置为处于第一模式的输出驱动器，并且在第二模式中将Ivenin等效终止。

7. 发明申请

US20080170607A1 TRANSCEIVER WITH FAULT TOLERANT DRIVER 有权
标题翻译：带有故障驱动器的收发器
公开(公告)号：US20080170607A1
公开(公告)日：2008-07-17
申请号：US11971682
申请日：2008-01-09
申请人： Todd Randazzo
发明人： Todd Randazzo
IPC分类号： H04B1/38
CPC分类号： H04L25/0278
摘要： A fault tolerant driver circuit includes a data output driver that receives an enable input and that includes a transistor formed on an isolation well. A well bias circuit provides a first well bias to the isolation well. The well bias circuit includes voltage-controlled impedances that are controlled by a voltage of the data output line, the enable input and a supply voltage. The voltage-controlled impedances connect the first well bias alternatively to: a common conductor through a first impedance when the supply voltage is ON and the enable input is ON; and a second impedance when the supply voltage is on and enable is OFF.
摘要翻译：容错驱动器电路包括接收使能输入并且包括形成在隔离阱上的晶体管的数据输出驱动器。阱偏置电路为隔离阱提供了第一阱偏置。阱偏置电路包括由数据输出线的电压，使能输入和电源电压控制的电压控制阻抗。当电源电压为ON并且使能输入为ON时，电压控制阻抗交替地将第一阱偏压连接到：通过第一阻抗的公共导体; 并且当电源电压接通并使能时为第二阻抗。

8. 发明授权

US07948275B2 Transceiver with fault tolerant driver 有权
标题翻译：收发器具有容错驱动
公开(公告)号：US07948275B2
公开(公告)日：2011-05-24
申请号：US11971682
申请日：2008-01-09
申请人： Todd Randazzo
发明人： Todd Randazzo
IPC分类号： H03B1/00
CPC分类号： H04L25/0278
摘要： A fault tolerant driver circuit includes a data output driver that receives an enable input and that includes a transistor formed on an isolation well. A well bias circuit provides a first well bias to the isolation well. The well bias circuit includes voltage-controlled impedances that are controlled by a voltage of the data output line, the enable input and a supply voltage. The voltage-controlled impedances connect the first well bias alternatively to: a common conductor through a first impedance when the supply voltage is ON and the enable input is ON; and a second impedance when the supply voltage is on and enable is OFF.
摘要翻译：容错驱动器电路包括接收使能输入并且包括形成在隔离阱上的晶体管的数据输出驱动器。阱偏置电路为隔离阱提供了第一阱偏置。阱偏置电路包括由数据输出线的电压，使能输入和电源电压控制的电压控制阻抗。当电源电压为ON并且使能输入为ON时，电压控制阻抗交替地将第一阱偏压连接到：通过第一阻抗的公共导体; 并且当电源电压接通并使能时为第二阻抗。

9. 发明授权

US07876123B2 High speed multiple memory interface I/O cell 有权
标题翻译：高速多存储器接口I / O单元
公开(公告)号：US07876123B2
公开(公告)日：2011-01-25
申请号：US12109497
申请日：2008-04-25
申请人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
发明人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
IPC分类号： H03K17/16
CPC分类号： G11C29/02 , G11C7/04 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2029/5602 , G11C2207/105 , G11C2207/2254
摘要： An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.
摘要翻译：输入/输出（I / O）单元包括一个或多个可驱动器段和一个或多个片上终端（ODT）能力段。 I / O单元可以被配置为处于第一模式的输出驱动器，并且在第二模式中将Ivenin等效终止。

10. 发明申请

US20090091349A1 High speed multiple memory interface I/O cell 有权
标题翻译：高速多存储器接口I / O单元
公开(公告)号：US20090091349A1
公开(公告)日：2009-04-09
申请号：US12109497
申请日：2008-04-25
申请人： Dharmesh Bhakta , Hong-Him Lin , Cheng-Gang Kong , Todd Randazzo
发明人： Dharmesh Bhakta , Hong-Him Lin , Cheng-Gang Kong , Todd Randazzo
IPC分类号： H03K19/003 , H03K19/0175 , G01R35/00
CPC分类号： G11C29/02 , G11C7/04 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2029/5602 , G11C2207/105 , G11C2207/2254
摘要： An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.
摘要翻译：输入/输出（I / O）单元包括一个或多个可驱动器段和一个或多个片上终端（ODT）能力段。 I / O单元可以被配置为处于第一模式的输出驱动器，并且在第二模式中将Ivenin等效终止。

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