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1. 发明申请

US20090091349A1 High speed multiple memory interface I/O cell 有权
标题翻译：高速多存储器接口I / O单元
公开(公告)号：US20090091349A1
公开(公告)日：2009-04-09
申请号：US12109497
申请日：2008-04-25
申请人： Dharmesh Bhakta , Hong-Him Lin , Cheng-Gang Kong , Todd Randazzo
发明人： Dharmesh Bhakta , Hong-Him Lin , Cheng-Gang Kong , Todd Randazzo
IPC分类号： H03K19/003 , H03K19/0175 , G01R35/00
CPC分类号： G11C29/02 , G11C7/04 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2029/5602 , G11C2207/105 , G11C2207/2254
摘要： An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.
摘要翻译：输入/输出（I / O）单元包括一个或多个可驱动器段和一个或多个片上终端（ODT）能力段。 I / O单元可以被配置为处于第一模式的输出驱动器，并且在第二模式中将Ivenin等效终止。

2. 发明授权

US08324927B2 High speed multiple memory interface I/O cell 有权
标题翻译：高速多存储器接口I / O单元
公开(公告)号：US08324927B2
公开(公告)日：2012-12-04
申请号：US12970071
申请日：2010-12-16
申请人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
发明人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
IPC分类号： H03K17/16
CPC分类号： G11C29/02 , G11C7/04 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2029/5602 , G11C2207/105 , G11C2207/2254
摘要： An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.
摘要翻译：输入/输出（I / O）单元包括一个或多个可驱动器段和一个或多个片上终端（ODT）能力段。 I / O单元可以被配置为处于第一模式的输出驱动器，并且在第二模式中将Ivenin等效终止。

3. 发明申请

US20110084725A1 HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL 有权
标题翻译：高速多存储器接口I / O单元
公开(公告)号：US20110084725A1
公开(公告)日：2011-04-14
申请号：US12970071
申请日：2010-12-16
申请人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
发明人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
IPC分类号： H03K19/003
CPC分类号： G11C29/02 , G11C7/04 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2029/5602 , G11C2207/105 , G11C2207/2254
摘要： An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.
摘要翻译：输入/输出（I / O）单元包括一个或多个可驱动器段和一个或多个片上终端（ODT）能力段。 I / O单元可以被配置为处于第一模式的输出驱动器，并且在第二模式中将Ivenin等效终止。

4. 发明授权

US07876123B2 High speed multiple memory interface I/O cell 有权
标题翻译：高速多存储器接口I / O单元
公开(公告)号：US07876123B2
公开(公告)日：2011-01-25
申请号：US12109497
申请日：2008-04-25
申请人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
发明人： Dharmesh Bhakta , Hong-Him Lim , Cheng-Gang Kong , Todd Randazzo
IPC分类号： H03K17/16
CPC分类号： G11C29/02 , G11C7/04 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2029/5602 , G11C2207/105 , G11C2207/2254
摘要： An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.
摘要翻译：输入/输出（I / O）单元包括一个或多个可驱动器段和一个或多个片上终端（ODT）能力段。 I / O单元可以被配置为处于第一模式的输出驱动器，并且在第二模式中将Ivenin等效终止。

5. 发明申请

US20120194248A1 NON-LINEAR COMMON COARSE DELAY SYSTEM AND METHOD FOR DELAYING DATA STROBE 有权
标题翻译：非线性常规延迟系统和延迟数据结构的方法
公开(公告)号：US20120194248A1
公开(公告)日：2012-08-02
申请号：US13016472
申请日：2011-01-28
申请人： Terence J. Magee , Christopher D. Paulson , Cheng-Gang Kong
发明人： Terence J. Magee , Christopher D. Paulson , Cheng-Gang Kong
IPC分类号： H03H11/26 , G01R29/00 , G06F19/00 , G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222
摘要： A non-linear common coarse delay system and method for delaying a data strobe in order to preserve fine delay accuracy and compensate PVT (Process, Voltage, and Temperature) variation effects. A common coarse delay and a fine delay can be initialized to a quarter-cycle delay for shifting a read output DQS (Data Queue Strobe) associated with a memory device in order to sample a read output DQ (Data Queue) within a physical layer. The fine delay can be programmed from minimum to maximum delay with fixed linear increments at each delay step in order to determine the resolution and accuracy of the delay. An optimum delay size of both the coarse and the fine delay can be determined based on an application slowest frequency of operation. A spare coarse delay and a functional coarse delay can be trained in association with a spare fine delay and the functional fine delay can be updated in order to monitor the process, voltage, and temperature variation effects.
摘要翻译：用于延迟数据选通的非线性公共粗延迟系统和方法，以便保持精细的延迟精度并补偿PVT（过程，电压和温度）变化的影响。普通粗延迟和精细延迟可以初始化为四分之一周期的延迟，用于移位与存储器件相关联的读输出DQS（数据队列选通），以便对物理层内的读输出DQ（数据队列）进行采样。在每个延迟步骤中，精细延迟可以从最小到最大延迟编程为固定的线性增量，以便确定延迟的分辨率和精度。基于应用最慢的操作频率，可以确定粗略和精细延迟的最佳延迟大小。可以与备用精细延迟相关联地训练备用粗延迟和功能粗延迟，并且可以更新功能精细延迟以便监视过程，电压和温度变化效应。

6. 发明授权

US07839716B2 Apparatus and systems for VT invariant DDR3 SDRAM write leveling 有权
标题翻译：用于VT不变式DDR3 SDRAM写入调平的装置和系统
公开(公告)号：US07839716B2
公开(公告)日：2010-11-23
申请号：US12339232
申请日：2008-12-19
申请人： Cheng-Gang Kong , Thomas Hughes
发明人： Cheng-Gang Kong , Thomas Hughes
IPC分类号： G11C8/16
CPC分类号： G11C8/18 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C8/12
摘要： Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial write-leveling procedure determines the correct skew and programs a register file in the skew adjustment circuit. The register file includes a register for each of multiple ranks in the DDR3 memory. The values in each register serve to control selection of alignment of the data related signals to align with one of multiple phase shifted versions of a 1× DDR3 clock signal. The phase shifted clock signals are generated by clock divider circuits from a 2× DDR clock signal and use of a single fixed delay line approximating ⅛ of a 1× DDR3 clock period.
摘要翻译：用于改进DDR3存储器子系统中的PVT不变快速级别切换的装置和系统。时钟偏移控制电路设置在存储器控制器和DDR3 SDRAM存储器子系统之间，以调整DDR3时钟信号与数据相关信号（例如DQ和/或DQS）之间的偏差。初始写入调平过程确定正确的偏移，并对偏斜调整电路中的寄存器文件进行编程。寄存器文件包括DDR3存储器中多个级别中的每一个的寄存器。每个寄存器中的值用于控制数据相关信号的对准选择，以与1×DDR3时钟信号的多个相移版本中的一个对准。相移时钟信号由时钟分频器电路从2×DDR时钟信号产生，并使用近似1×DDR3时钟周期的单个固定延迟线。

7. 发明申请

US20080068911A1 System and method for providing swap path voltage and temperature compensation 失效
标题翻译：提供交换路径电压和温度补偿的系统和方法
公开(公告)号：US20080068911A1
公开(公告)日：2008-03-20
申请号：US11523139
申请日：2006-09-19
申请人： Thomas Hughes , Cheng-Gang Kong
发明人： Thomas Hughes , Cheng-Gang Kong
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2254
摘要： The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method further includes swapping the offline data path with the online data path. Further, swapping occurs automatically without interruption of data flow along the data paths.
摘要翻译：本发明是数据路径电压和温度补偿的方法。该方法包括配置脱机数据路径以匹配在线数据路径。该方法还包括补偿离线数据路径的电压和温度变化。该方法还包括将离线数据路径与在线数据路径进行交换。此外，交换自动发生而不中断沿数据路径的数据流。

8. 发明申请

US20060288175A1 Feedback programmable data strobe enable architecture for DDR memory applications 有权
标题翻译：用于DDR存储器应用的反馈可编程数据选通使能架构
公开(公告)号：US20060288175A1
公开(公告)日：2006-12-21
申请号：US11154401
申请日：2005-06-16
申请人： Hui-Yin Seto , Derrick Butt , Cheng-Gang Kong
发明人： Hui-Yin Seto , Derrick Butt , Cheng-Gang Kong
IPC分类号： G06F13/00
CPC分类号： G06F13/4239
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to read and write data through a plurality of input/output lines. The second circuit may include a plurality of sections. Each section may be configured to present a control signal to a load output line and receive a feedback of the control signal through a load input line. The load input line and the load output line of each of the sections may be connected to a load circuit configured to match a respective memory load connected to each of the plurality of input/output lines.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为通过多个输入/输出线读取和写入数据。第二电路可以包括多个部分。每个部分可以被配置为向负载输出线呈现控制信号，并通过负载输入线接收控制信号的反馈。每个部分的负载输入线和负载输出线可以连接到被配置为匹配连接到多个输入/输出线中的每一个的相应存储器负载的负载电路。

9. 发明申请

US20060132210A1 Wide-range programmable delay line 有权
公开(公告)号：US20060132210A1
公开(公告)日：2006-06-22
申请号：US11021361
申请日：2004-12-22
申请人： Cheng-Gang Kong , Victor Suen
发明人： Cheng-Gang Kong , Victor Suen
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00071
摘要： An apparatus comprising an input section, a first delay circuit and a second delay circuit. The input section may be configured to present a first intermediate signal by selecting either (i) an input clock signal or (ii) a feedback of an output signal. The first delay circuit may be configured to generate a second intermediate signal by delaying the first intermediate signal by inserting one of a plurality of fixed delays in response to a first control signal. The second delay circuit may be configured to generate the output signal by delaying the second intermediate signal by inserting a programmable delay in response to a second control signal.

10. 发明授权

US4777588A General-purpose register file optimized for intraprocedural register allocation, procedure calls, and multitasking performance 失效
标题翻译：通用寄存器文件优化用于进行内部寄存器分配，过程调用和多任务性能
公开(公告)号：US4777588A
公开(公告)日：1988-10-11
申请号：US771311
申请日：1985-08-30
申请人： Brian W. Case , Rod G. Fleck , William M. Johnson , Cheng-Gang Kong , Ole Moller
发明人： Brian W. Case , Rod G. Fleck , William M. Johnson , Cheng-Gang Kong , Ole Moller
IPC分类号： G06F9/30 , G06F9/34 , G06F9/40 , G06F9/46 , G06F9/48 , G06F12/14
CPC分类号： G06F9/468 , G06F12/1458 , G06F9/4425 , G06F9/462
摘要： A high speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providing overlapping registers which are accessible to both procedures. Each procedure also has a set of "local" registers assigned to it which are inaccessible from other procedures. The register file is divided into a number of blocks and a protection register stores a word which proscribes access by a particular procedure or task to certain blocks. In this manner, an instruction processor using the register file can operate on multiple tasks maintaining the integrity of each from undesired changes occuring in the others.
摘要翻译：公开了一种适用于精简指令集计算机（RISC）的指令处理器所使用的高速寄存器文件，其优选地以有效的寄存器分配方法使用。寄存器文件通过动态地提供两个过程可访问的重叠寄存器来促进过程之间的参数传递。每个过程也有一组分配给它的“本地”寄存器，不能从其他过程访问。寄存器文件被分成多个块，并且保护寄存器存储一个单词，其禁止特定过程或任务访问某些块。以这种方式，使用寄存器文件的指令处理器可以对多个任务进行操作，从而保持每个任务的完整性，而不是在其他任务中发生不希望的变化。

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