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1. 发明申请

US20060043487A1 Bi-directional ESD protection circuit 有权
标题翻译：双向ESD保护电路
公开(公告)号：US20060043487A1
公开(公告)日：2006-03-02
申请号：US10926916
申请日：2004-08-26
申请人： Timothy Pauletti , Sameer Pendharkar , Wayne Chen , Jonathan Brodsky , Robert Steinhoff
发明人： Timothy Pauletti , Sameer Pendharkar , Wayne Chen , Jonathan Brodsky , Robert Steinhoff
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/7436 , H01L29/749 , H01L29/87 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.
摘要翻译：一种用于保护电路的输入/输出端子的静电放电（ESD）装置，该装置包括：第一晶体管，其具有耦合在电路的输入/输出（I / O）端子之间的集成硅控整流器（SCR）节点和第二晶体管，其具有耦合在所述节点和电源电压的负端子之间的集成硅控整流器，其中所述第一晶体管的所述硅控整流器响应于ESD ESD电压而触发，并且所述可硅可控整流器的第二晶体管响应于正的ESD电压而触发。

2. 发明授权

US08890248B2 Bi-directional ESD protection circuit 有权
标题翻译：双向ESD保护电路
公开(公告)号：US08890248B2
公开(公告)日：2014-11-18
申请号：US10926916
申请日：2004-08-26
申请人： Timothy Patrick Pauletti , Sameer Pendharkar , Wayne Tien-Feng Chen , Jonathan Brodsky , Robert Steinhoff
发明人： Timothy Patrick Pauletti , Sameer Pendharkar , Wayne Tien-Feng Chen , Jonathan Brodsky , Robert Steinhoff
IPC分类号： H01L23/62 , H01L29/74 , H01L27/02 , H01L29/87 , H01L29/749
CPC分类号： H01L27/0262 , H01L29/7436 , H01L29/749 , H01L29/87 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.
摘要翻译：一种用于保护电路的输入/输出端子的静电放电（ESD）装置，该装置包括：第一晶体管，其具有耦合在电路的输入/输出（I / O）端子之间的集成硅控整流器（SCR）节点和第二晶体管，其具有耦合在所述节点和电源电压的负端子之间的集成硅控整流器，其中所述第一晶体管的所述硅控整流器响应于ESD ESD电压而触发，并且所述可硅可控整流器的第二晶体管响应于正的ESD电压而触发。

3. 发明申请

US20060186467A1 System and method for making a LDMOS device with electrostatic discharge protection 有权
标题翻译：制造具有静电放电保护功能的LDMOS器件的系统和方法
公开(公告)号：US20060186467A1
公开(公告)日：2006-08-24
申请号：US11063312
申请日：2005-02-21
申请人： Sameer Pendharkar , Jonathan Brodsky
发明人： Sameer Pendharkar , Jonathan Brodsky
IPC分类号： H01L29/76
CPC分类号： H01L29/66681 , H01L27/088 , H01L29/086 , H01L29/42368 , H01L29/7436 , H01L29/749 , H01L29/7816
摘要： A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.
摘要翻译：半导体器件包括一个或多个LDMOS晶体管和一个更多的SCR-LDMOS晶体管。每个LDMOS晶体管包括第一导电类型的LDMOS阱，在LDMOS阱中形成的第二导电类型的LDMOS源极区，以及由LDMOS阱的LDMOS漂移区分离的第二导电类型的LDMOS漏极区，第二导电类型。每个SCR-LDMOS晶体管包括第一导电类型的SCR-LDMOS阱，形成在SCR-LDMOS阱中的第二导电类型的SCR-LDMOS源区，第二导电类型的SCR-LDMOS漏极区和 SCR-LDMOS漏区和SCR-LDMOS漂移区之间的第一导电类型的阳极区。阳极区域通过第二导电类型的SCR-LDMOS漂移区与SCR-LDMOS阱分离。

4. 发明授权

US09385196B2 Fast switching IGBT with embedded emitter shorting contacts and method for making same 有权
标题翻译：具有嵌入式发射极短路触点的快速开关IGBT及其制造方法
公开(公告)号：US09385196B2
公开(公告)日：2016-07-05
申请号：US13611653
申请日：2012-09-12
申请人： Jacek Korec , John Manning Savidge Neilson , Sameer Pendharkar
发明人： Jacek Korec , John Manning Savidge Neilson , Sameer Pendharkar
IPC分类号： H01L29/739 , H01L21/331 , H01L29/08 , H01L29/66
CPC分类号： H01L29/66333 , H01L21/02532 , H01L21/02595 , H01L21/32053 , H01L29/0834 , H01L29/7395
摘要： Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or gown epitaxial silicon for controlled drift region thickness and fast switching speed.
摘要翻译：具有集成电路的具有集成发射极短路的高压IGBT和使用晶片接合或外延硅的外延硅的制造工艺用于控制漂移区厚度和快速开关速度。

5. 发明授权

US08872273B2 Integrated gate controlled high voltage divider 有权
标题翻译：集成门控高压分压器
公开(公告)号：US08872273B2
公开(公告)日：2014-10-28
申请号：US13567340
申请日：2012-08-06
申请人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
发明人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
IPC分类号： H01L27/11 , H01L27/06 , H01L49/02
CPC分类号： H01L28/20 , H01L27/0629
摘要： An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.
摘要翻译：一种集成电路，其包含栅极控制分压器，该栅极控制分压器具有与场效应晶体管上的上电阻串联的晶体管开关，与下电阻串联。电阻器漂移层设置在上电阻器下方，并且晶体管开关包括与电阻器漂移层相邻的开关漂移层，由防止漂移层之间的击穿的区域分开。开关漂移层为晶体管开关提供了扩展的漏极或集电极。分压器的感测端子耦合到晶体管的源极或发射极节点和下电阻器。输入端子耦合到上电阻器和电阻漂移层。形成包含栅极控制分压器的集成电路的工艺。

6. 发明申请

US20130285137A1 PROGRAMMABLE SCR FOR LDMOS ESD PROTECTION 有权
标题翻译：用于LDMOS ESD保护的可编程SCR
公开(公告)号：US20130285137A1
公开(公告)日：2013-10-31
申请号：US13460523
申请日：2012-04-30
申请人： Sameer Pendharkar , Suhail Murtaza , Juergen Wittmann
发明人： Sameer Pendharkar , Suhail Murtaza , Juergen Wittmann
IPC分类号： H01L29/78
CPC分类号： H01L29/0692 , H01L29/87
摘要： A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.
摘要翻译：用于DMOS晶体管的保护电路包括阳极电路，其具有在第二导电类型（310,312）的第一轻掺杂区域内形成并电连接的第一导电类型的第一重掺杂区域（314）。在第二导电类型（304）的第二重掺杂区域内具有第一导电类型（700）的多个第三重掺杂区域的阴极电路。第一引线（202）连接到每个第三重掺杂区域（704），并且通过每两个第三重掺杂区域之间的至少三个间隔开的连接（702）连接到第二重掺杂区域。在阳极电路和阴极电路之间连接有SCR（400,402）。 DMOS晶体管具有连接到阳极电路的漏极（310,312,316）和连接到阴极电路的源极（304）。

7. 发明申请

US20120112275A1 Drain Extended CMOS with Counter-Doped Drain Extension 有权
标题翻译：排水扩展CMOS与反掺杂漏极扩展
公开(公告)号：US20120112275A1
公开(公告)日：2012-05-10
申请号：US13288690
申请日：2011-11-03
申请人： Philipp Steinmann , Amitava Chatterjee , Sameer Pendharkar
发明人： Philipp Steinmann , Amitava Chatterjee , Sameer Pendharkar
IPC分类号： H01L29/78 , G06F17/50
CPC分类号： H01L29/66681 , G06F17/5081 , H01L29/0878 , H01L29/1045 , H01L29/161 , H01L29/167 , H01L29/66659 , H01L29/66734 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L29/861
摘要： An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
摘要翻译：一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。

8. 发明申请

US20110108914A1 MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION 有权
公开(公告)号：US20110108914A1
公开(公告)日：2011-05-12
申请号：US13006566
申请日：2011-01-14
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L29/78
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

9. 发明授权

US07883973B2 Method of forming semiconductor wells 有权
标题翻译：形成半导体井的方法
公开(公告)号：US07883973B2
公开(公告)日：2011-02-08
申请号：US12335756
申请日：2008-12-16
申请人： Seetharaman Sridar , Marie Denison , Sameer Pendharkar
发明人： Seetharaman Sridar , Marie Denison , Sameer Pendharkar
IPC分类号： H01L21/336
CPC分类号： H01L21/2652
摘要： A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.
摘要翻译：提供形成半导体器件的方法。提供具有形成在其上的电介质层的衬底。电介质层覆盖衬底的受保护区域，并且具有暴露衬底的第一未受保护区域的第一开口。第一掺杂剂通过电介质层中的第一开口注入第一未保护区域，并通过电介质层注入保护区域。

10. 发明申请

US20100264486A1 FIELD PLATE TRENCH MOSFET TRANSISTOR WITH GRADED DIELECTRIC LINER THICKNESS 审中-公开
标题翻译：具有分级电介质衬里厚度的现场板式TRENCH MOSFET晶体管
公开(公告)号：US20100264486A1
公开(公告)日：2010-10-21
申请号：US12426717
申请日：2009-04-20
申请人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
发明人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66719 , H01L29/66734
摘要： An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region.
摘要翻译：电子器件具有形成在半导体层中的多个沟槽。垂直漂移区域位于沟槽之间和相邻的沟槽之间。电极位于每个沟槽内，电极具有栅电极部分和场板部分。梯度场板电介质位于场板部分和垂直漂移区之间。

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