专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07883973B2 Method of forming semiconductor wells 有权
标题翻译：形成半导体井的方法
公开(公告)号：US07883973B2
公开(公告)日：2011-02-08
申请号：US12335756
申请日：2008-12-16
申请人： Seetharaman Sridar , Marie Denison , Sameer Pendharkar
发明人： Seetharaman Sridar , Marie Denison , Sameer Pendharkar
IPC分类号： H01L21/336
CPC分类号： H01L21/2652
摘要： A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.
摘要翻译：提供形成半导体器件的方法。提供具有形成在其上的电介质层的衬底。电介质层覆盖衬底的受保护区域，并且具有暴露衬底的第一未受保护区域的第一开口。第一掺杂剂通过电介质层中的第一开口注入第一未保护区域，并通过电介质层注入保护区域。

2. 发明申请

US20100148125A1 METHOD OF FORMING SEMICONDUCTOR WELLS 有权
标题翻译：形成半导体阱的方法
公开(公告)号：US20100148125A1
公开(公告)日：2010-06-17
申请号：US12335756
申请日：2008-12-16
申请人： Seetharaman Sridar , Marie Denison , Sameer Pendharkar
发明人： Seetharaman Sridar , Marie Denison , Sameer Pendharkar
IPC分类号： H01B1/02 , H01L21/425
CPC分类号： H01L21/2652
摘要： A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.
摘要翻译：提供形成半导体器件的方法。提供具有形成在其上的电介质层的衬底。电介质层覆盖衬底的受保护区域，并且具有暴露衬底的第一未受保护区域的第一开口。第一掺杂剂通过电介质层中的第一开口注入第一未保护区域，并通过电介质层注入保护区域。

3. 发明授权

US09806190B2 High voltage drain extension on thin buried oxide SOI 有权
公开(公告)号：US09806190B2
公开(公告)日：2017-10-31
申请号：US13282305
申请日：2011-10-26
申请人： Marie Denison , Philip L. Hower , Sameer Pendharkar
发明人： Marie Denison , Philip L. Hower , Sameer Pendharkar
IPC分类号： H01L29/78 , H01L21/336 , H01L27/12 , H01L29/10 , H01L29/861 , H01L27/06
CPC分类号： H01L29/7824 , H01L27/0629 , H01L27/1203 , H01L29/1087 , H01L29/7818 , H01L29/7835 , H01L29/861
摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

4. 发明授权

US08853029B2 Method of making vertical transistor with graded field plate dielectric 有权
标题翻译：制造具有梯度场板电介质的垂直晶体管的方法
公开(公告)号：US08853029B2
公开(公告)日：2014-10-07
申请号：US13188162
申请日：2011-07-21
申请人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
发明人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66719 , H01L29/66734
摘要： An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.
摘要翻译：电子器件具有形成在半导体层中的多个沟槽。垂直漂移区域位于沟槽之间和相邻的沟槽之间。电极位于每个沟槽内，电极具有栅电极部分和场板部分。在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。

5. 发明申请

US20120104497A1 HIGH VOLTAGE DRAIN EXTENSION ON THIN BURIED OXIDE SOI 有权
标题翻译：稀土氧化物SOI上的高压漏电延伸
公开(公告)号：US20120104497A1
公开(公告)日：2012-05-03
申请号：US13282305
申请日：2011-10-26
申请人： Marie Denison , Philip L. Hower , Sameer Pendharkar
发明人： Marie Denison , Philip L. Hower , Sameer Pendharkar
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L27/0629 , H01L27/1203 , H01L29/1087 , H01L29/7818 , H01L29/7835 , H01L29/861
摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).
摘要翻译： SOI衬底上的集成电路，其包含在漏极（n沟道）或体区（p沟道）中具有穿通衬底二极管的扩展漏极MOS晶体管，使得漏极或体区域通过pn耦合到处理晶片交界处在SOI衬底上的集成电路，其包含通过pn结耦合到处理晶片的漏极（n沟道）或体区（p沟道）中的贯穿衬底二极管的延伸漏极MOS晶体管，其与排水或身体区域。在包含漏极（n沟道）或体区（p沟道）中的贯通衬底二极管的延伸漏极MOS晶体管的SOI衬底上形成集成电路的工艺。

6. 发明申请

US20110111569A1 MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION 有权
标题翻译：具有栅极扩展的MOS晶体管与漏极扩展场绝缘相邻
公开(公告)号：US20110111569A1
公开(公告)日：2011-05-12
申请号：US13006589
申请日：2011-01-14
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L21/336
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.
摘要翻译：一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。体阱和源极扩散区域与栅极沟槽的底表面重叠。一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。埋层是与漂移区相同的导电类型。形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

7. 发明申请

US20110076822A1 LATERAL METAL OXIDE SEMICONDUCTOR DRAIN EXTENSION DESIGN 有权
标题翻译：侧向金属氧化物半导体漏斗扩展设计
公开(公告)号：US20110076822A1
公开(公告)日：2011-03-31
申请号：US12961885
申请日：2010-12-07
申请人： Marie Denison , Seetharaman Sridhar , Sameer Pendharkar
发明人： Marie Denison , Seetharaman Sridhar , Sameer Pendharkar
IPC分类号： H01L21/336
CPC分类号： H01L29/402 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.
摘要翻译：包括源极和漏极区域105,107以及绝缘区域115和板状结构140的半导体器件100.源极和漏极区域在半导体衬底110上或半导体衬底110中。绝缘区域在半导体衬底上或半导体衬底中并且位于源极和漏极区域。绝缘区域具有薄层120和厚层122.厚层包括彼此分离并且跨越源极和漏极区域之间的长度135延伸的多个绝缘条132。板结构位于源极和漏极区之间，其中板结构位于薄层上，厚层的部分，板结构具有一个或多个导电带143，其直接位于多个绝缘条纹

8. 发明授权

US07893499B2 MOS transistor with gate trench adjacent to drain extension field insulation 有权
标题翻译： MOS晶体管，栅极沟槽与漏极延伸场绝缘相邻
公开(公告)号：US07893499B2
公开(公告)日：2011-02-22
申请号：US12417810
申请日：2009-04-03
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L29/66
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.
摘要翻译：一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。体阱和源极扩散区域与栅极沟槽的底表面重叠。一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。埋层是与漂移区相同的导电类型。形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

9. 发明申请

US20100252882A1 MOS Transistor with Gate Trench Adjacent to Drain Extension Field Insulation 有权
标题翻译： MOS晶体管，栅极沟槽与漏极延伸场绝缘相邻
公开(公告)号：US20100252882A1
公开(公告)日：2010-10-07
申请号：US12417810
申请日：2009-04-03
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.
摘要翻译：一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。体阱和源极扩散区域与栅极沟槽的底表面重叠。一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。埋层是与漂移区相同的导电类型。形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

10. 发明授权

US08580650B2 Lateral superjunction extended drain MOS transistor 有权
标题翻译：横向超结延长漏极MOS晶体管
公开(公告)号：US08580650B2
公开(公告)日：2013-11-12
申请号：US13284054
申请日：2011-10-28
申请人： Marie Denison , Sameer Pendharkar
发明人： Marie Denison , Sameer Pendharkar
IPC分类号： H01L21/76
CPC分类号： H01L29/7816 , H01L21/76224 , H01L29/0634 , H01L29/0649 , H01L29/0692 , H01L29/0696 , H01L29/0882 , H01L29/4236 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.
摘要翻译：一种集成电路，其包含在漂移区域中具有深半导体（SC）RESURF沟槽的扩展漏极MOS晶体管，其中每个深的SC RESURF沟槽在与漂移区接触的沟槽的侧壁处具有半导体RESURF层。半导体RESURF层具有与漂移区相反的导电类型。深的SC RESURF沟槽具有至少5：1的深度：宽度比，并且不延伸穿过漂移区域的底部表面。通过蚀刻尺寸不足的沟槽和反向掺杂侧壁区以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。通过蚀刻沟槽并在侧壁区域上生长外延层以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式