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    • 1. 发明授权
    • Modular high-capacity solid-state mass data storage device including
controller/memory modules arranged in parallel channels
    • 模块化大容量固体大容量数据存储装置,其包括以并行通道排列的控制器/存储器模块
    • US5471603A
    • 1995-11-28
    • US963192
    • 1992-10-19
    • Timothy A. YokoteEric L. UptonArthur G. EnyedyGrant J. StocktonDirk K. Brandis
    • Timothy A. YokoteEric L. UptonArthur G. EnyedyGrant J. StocktonDirk K. Brandis
    • B64D47/00G06F11/00G06F11/10G06F11/16G06F11/20G06F12/16G06F13/00G06F13/12
    • G11C5/02G11C5/04
    • A modular solid-state mass data storage device providing high-density, high-capacity storage of data employs a modular pipeline architecture in which a distributed array of controller/memory modules is arranged in parallel controller/memory channels on one or more controller/memory cards, each controller/memory channel having first and last controller/memory modules. The modular storage device also includes a data format module, and first and second busses connecting outputs of the data format module to inputs of each of the first and last controller/memory modules. The first bus also connects outputs of the last controller/memory module in each channel back to an input of the data format modules. The modular pipeline architecture allows the number of controller/memory modules in each channel to be easily configured to accommodate any required storage size, while the number of controller/memory channels can be configured to accommodate any required storage size and transfer rate, without increasing latency time. The modular pipeline architecture also greatly simplifies the complexity of the memory controllers, and high-density packaging of the controller/memory modules provides compact storage for large amounts of data. The mass data storage device may be used as a random access memory (RAM) disk or for any other application requiring high-density, high-capacity mass data storage devices.
    • 提供高密度,大容量数据存储的模块化固态大容量数据存储设备采用模块化流水线架构,其中控制器/存储器模块的分布式阵列被布置在一个或多个控制器/存储器上的并行控制器/存储器通道中 卡,每个控制器/存储器通道具有第一和最后一个控制器/存储器模块。 模块化存储设备还包括数据格式模块,以及将数据格式模块的输出连接到第一和最后一个控制器/存储器模块中的每一个的输入的第一和第二总线。 第一个总线还将每个通道中的最后一个控制器/存储器模块的输出连接回数据格式模块的输入。 模块化流水线架构允许每个通道中的控制器/内存模块的数量容易配置,以适应任何所需的存储大小,而控制器/内存通道的数量可以配置为适应任何所需的存储大小和传输速率,而不会增加延迟 时间。 模块化管道架构还大大简化了存储器控制器的复杂性,并且控制器/存储器模块的高密度封装为大量数据提供了紧凑的存储。 大容量数据存储设备可以用作随机存取存储器(RAM)盘或用于需要高密度,大容量大容量数据存储设备的任何其它应用。
    • 2. 发明授权
    • Modular high-capacity solid-state mass data storage device for video
servers including a switch for simultaneous multi-viewer access
    • 用于视频服务器的模块化大容量固态大容量数据存储设备,包括用于同时多浏览器访问的交换机
    • US5651129A
    • 1997-07-22
    • US611353
    • 1996-03-06
    • Timothy A. YokoteGrant J. StocktonEric L. UptonArthur G. EnyedyDirk K. Brandis
    • Timothy A. YokoteGrant J. StocktonEric L. UptonArthur G. EnyedyDirk K. Brandis
    • G06F12/00G06F11/00G11C5/00H04L29/06H04N5/00H04N5/907H04N7/173G06F13/00H04N7/10
    • H04N21/21815H04L29/06H04N5/907H04N7/17318H04N7/17336
    • A modular solid-state mass data storage device providing high-density, high capacity storage of numerous full-length movies for video server applications. The mass data storage device employs a modular pipeline architecture in which a distributed array of controller/memory modules is arranged in parallel controller/memory channels on one or more controller/memory cards. The modular pipeline architecture, in which each controller/memory channel has multiple controller/memory modules connected in a serial chain by address, data and control buses, allows the number of controller/memory modules in each channel and the number of controller/memory channels to be selected to accommodate a desired storage size and transfer rate, without an undesirably high latency time. An asynchronous transfer mode (ATM) switch allows multiple viewers to access the movies stored in the mass data storage device with independent video cassette recorder (VCR)-like control of the movie being watched. In a disclosed embodiment, the controller/memory modules in each channel are connected to first and second buses which extend from a data format module, the first bus also extending from the last controller/memory modules in each channel back to the data format module. The data format module provides data formatting, synchronization and error correction for the stored movies. In the disclosed embodiment, each controller/memory module includes an array of dynamic random access memory (DRAM) chips, and multiple controller/memory modules are packaged in standard memory module packages, such as single in-line memory module (SIMM) packages.
    • 模块化固态大容量数据存储设备,为视频服务器应用提供高密度,高容量存储多种全长电影。 大容量数据存储设备采用模块化流水线架构,其中控制器/存储器模块的分布式阵列被布置在一个或多个控制器/存储卡上的并行控制器/存储器通道中。 模块化管道架构,其中每个控制器/存储器通道具有通过地址,数据和控制总线连接在串行链路中的多个控制器/存储器模块,允许每个通道中的控制器/存储器模块的数量以及控制器/存储器通道的数量 被选择以适应期望的存储大小和传送速率,而没有不期望的高等待时间。 异步传输模式(ATM)交换机允许多个观看者使用独立的录像机(VCR)来控制存储在大容量数据存储设备中的电影,如对正在观看的电影的控制。 在公开的实施例中,每个通道中的控制器/存储器模块连接到从数据格式模块延伸的第一和第二总线,第一总线也从每个通道中的最后一个控制器/存储器模块延伸回数据格式模块。 数据格式模块为存储的电影提供数据格式化,同步和纠错。 在所公开的实施例中,每个控制器/存储器模块包括动态随机存取存储器(DRAM)芯片的阵列,并且多个控制器/存储器模块被封装在诸如单列直插存储器模块(SIMM)封装的标准存储器模块封装中。
    • 4. 发明授权
    • Method and apparatus for adaptively compensating for an inaccuracy in an analog-to-digital converter
    • 用于自适应地补偿模数转换器中的不精确度的方法和装置
    • US06690310B1
    • 2004-02-10
    • US10366234
    • 2003-02-13
    • Eric L. Upton
    • Eric L. Upton
    • H03M106
    • H03M1/0604H03M1/44
    • In an analog-to-digital converter (100), a method and apparatus compare (302) an analog input signal (102) with a reference signal (108) to generate a decision signal (110), and sum (304) the analog input signal with a control value (130) whose magnitude is determined by an accumulated value (126), and whose sign is determined by the decision signal, thereby generating an error signal (114). The method and apparatus further calculate (306) a correlation value (118) between the error signal and the decision signal, and accumulate (308) the correlation value to produce the accumulated value, thereby adaptively compensating for an inaccuracy in the A/D converter.
    • 在模拟数字转换器(100)中,一种方法和装置将模拟输入信号(102)与参考信号(108)进行比较(302)以产生判决信号(110),并且(304)模拟 输入信号具有其大小由累加值(126)确定的控制值(130),并且其符号由判定信号确定,从而产生误差信号(114)。 所述方法和装置进一步计算(306)误差信号与判定信号之间的相关值(118),并累积(308)相关值以产生累加值,从而自适应地补偿A / D转换器中的不准确性 。
    • 6. 发明授权
    • Optical devices employing an optical thresholder
    • 采用光阈值的光学器件
    • US06327399B1
    • 2001-12-04
    • US09444977
    • 1999-11-22
    • Richard A. FieldsBruce A. FergusonMark KintisElizabeth T. KunkeeLawrence J. LemboStephen R. PerkinsDavid L. RollinsEric L. Upton
    • Richard A. FieldsBruce A. FergusonMark KintisElizabeth T. KunkeeLawrence J. LemboStephen R. PerkinsDavid L. RollinsEric L. Upton
    • G02B626
    • G02F3/00G02F1/3515G02F1/3523
    • An optical device for use with an optical input beam comprises and optical thresholding device having a predetermined threshold level, and is positioned along an optical path defined by the propagation direction of the optical input beam. A source generates a control beam through the optical thresholding device, wherein if the combined intensity of the optical input beam and the control beam is large enough to exceed the threshold level of the thresholding device, the optical beam passes through he thresholding device. The thresholding device attenuates the optical beam as it passes therethrough. In a preferred embodiment, the optical thresholding device is a saturable absorber. When the device is configured as an optical comparator, the intensity of the optical input beam is large enough to exceed the threshold level of the thresholding device, the thresholding device saturates and turns transparent so that the control beam passes through the thresholding device as an optical indicator beam and the optical input beam passes through the thresholding device. When configured as an optical signal attenuator and the intensity of the optical input signal is negligible compared to that of the control beam the combined intensity of the optical input signal and the control beam do not saturate the thresholding device.
    • 用于光输入光束的光学装置包括具有预定阈值电平的光阈值装置,并且沿着由光输入光束的传播方向限定的光路定位。 源通过光阈值设备产生控制光束,其中如果光输入光束和控制光束的组合强度足够大以超过阈值设备的阈值电平,则光束通过阈值设备。 阈值装置在光束通过时衰减光束。 在优选实施例中,光阈值设备是可饱和吸收器。 当该设备被配置为光学比较器时,光输入光束的强度足够大以超过阈值设备的阈值电平,阈值设备饱和并变透明,使得控制光束作为光学器件通过阈值设备 指示光束和光输入光束通过阈值设备。 配置为光信号衰减器时,光输入信号的强度与控制光束的强度相比可忽略不计,光输入信号和控制光束的组合强度不会使阈值设备饱和。
    • 7. 发明授权
    • Multiple channel control using orthogonally modulated coded drive signals
    • 使用正交调制编码驱动信号的多通道控制
    • US6167024A
    • 2000-12-26
    • US42928
    • 1998-03-17
    • Eric L. UptonMichael G. WickhamMartin P. Smith
    • Eric L. UptonMichael G. WickhamMartin P. Smith
    • G02B6/34H04J14/00H04B7/216
    • H04J14/005H04J14/007
    • An orthogonal pilot tone servo controller provides a servo control loop for each tap in a delay line processor where each servo acquires its independence from the other tap's servos utilizing an orthogonal code set modulated on top of the existing tap values. The orthogonal codes are attenuated in amplitude such that the code sets are transparent to the processed signals of interest, but the code's length enables each tap's servo controller to independently recover the tap's state from the aggregate of signals and codes through processing gain realized in each loop's recovery circuit. A plurality of taps can be thus be servo controlled simultaneously, providing for extremely wide bandwidth processes which can be performed accurately with digital controls.
    • 正交导频音调伺服控制器为延迟线处理器中的每个抽头提供伺服控制回路,其中每个伺服器利用在现有抽头值顶部调制的正交码集来获取其与另一抽头的伺服的独立性。 正交码在幅度上衰减,使得码集对于所处理的感兴趣的信号是透明的,但是代码的长度使得每个抽头的伺服控制器能够从信号和代码的集合中独立地恢复抽头的状态,通过每个循环中实现的处理增益 恢复电路。 因此,可以同时伺服控制多个抽头,从而提供可以用数字控制精确地执行的极宽带宽处理。
    • 9. 发明授权
    • Transmitter-receiver for use in broadband wireless access communications
systems
    • 用于宽带无线接入通信系统的发射机 - 接收机
    • US6115584A
    • 2000-09-05
    • US285308
    • 1999-04-02
    • Donald L. TaitEric L. UptonFranklin J. Bayuk
    • Donald L. TaitEric L. UptonFranklin J. Bayuk
    • H04B1/50H03D7/18H04B1/28H04B1/30H04B1/40H04Q7/32
    • H03D7/18H04B1/40H04B1/28H04B1/30
    • A transmitter-receiver includes a transmitting circuit for providing an output by converting the frequency of a transmission signal input thereto, a receiving circuit for providing an output by converting the frequency of a received signal input thereto, and a local oscillator which generates an oscillation signal having a local oscillating frequency based on a reference signal. A local oscillator signal splitter is connected to the local oscillator and splits the oscillation signal into substantially similar transmit and receive oscillation signals each at the local oscillating frequency. The local oscillator signal splitter supplies the transmit oscillation signal to the transmitting circuit and supplies the receive oscillation signal to the receiving circuit. The transmitting circuit converts the frequency of the transmission signal in accordance with said transmit oscillation signal, and the receiving circuit converts the frequency of the received signal in accordance with the receive oscillation signal.
    • 发射机 - 接收机包括通过转换输入的发送信号的频率来提供输出的发送电路,用于通过转换输入的接收信号的频率来提供输出的接收电路和产生振荡信号的本地振荡器 具有基于参考信号的本地振荡频率。 本地振荡器信号分离器连接到本地振荡器,并将振荡信号分成基本相似的发射和接收振荡信号,每个振荡信号在本地振荡频率处。 本地振荡器信号分离器将发送振荡信号提供给发送电路,并将接收振荡信号提供给接收电路。 发送电路根据所述发送振荡信号转换发送信号的频率,并且接收电路根据接收振荡信号转换接收信号的频率。
    • 10. 发明授权
    • Reconfigurable processor for executing successive function sequences in
a processor operation
    • 可重构处理器,用于在处理器操作中执行连续的功能序列
    • US6067615A
    • 2000-05-23
    • US556438
    • 1995-11-09
    • Eric L. Upton
    • Eric L. Upton
    • G06F15/78G06F15/00
    • G06F15/7867Y02B60/1207Y02B60/1225
    • A digital processor with reconfigurable architecture includes a processor input and a processor output. A library stores a plurality of related function sequences for executing a processor operation. Memory stores data as required by the function sequences. A configurable device is connected to the library and the memory and between the processor input and the processor output. The configurable device sequentially stores the function sequences from the library in a plurality of programmable gate arrays configurable by the function sequences. The configurable device reconfigures the programmable gate arrays with another of the function sequences to complete the processor operation.
    • 具有可重构架构的数字处理器包括处理器输入和处理器输出。 库存储用于执行处理器操作的多个相关功能序列。 内存根据功能序列的要求存储数据。 可配置的设备连接到库和存储器以及处理器输入和处理器输出之间。 可配置设备顺序地将来自库的功能序列存储在可由功能序列配置的多个可编程门阵列中。 可配置设备用另一个功能序列重新配置可编程门阵列,以完成处理器的操作。