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1. 发明授权

US08063449B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08063449B2
公开(公告)日：2011-11-22
申请号：US12626496
申请日：2009-11-25
申请人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
发明人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。在衬套上形成填充材料。填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

2. 发明授权

US07652336B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07652336B2
公开(公告)日：2010-01-26
申请号：US11834398
申请日：2007-08-06
申请人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
发明人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。在衬套上形成填充材料。填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

3. 发明申请

US20090039442A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090039442A1
公开(公告)日：2009-02-12
申请号：US11834398
申请日：2007-08-06
申请人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
发明人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
IPC分类号： H01L29/78 , H01L21/336 , H01L21/762
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。在衬套上形成填充材料。填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

4. 发明申请

US20100065922A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100065922A1
公开(公告)日：2010-03-18
申请号：US12626496
申请日：2009-11-25
申请人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
发明人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。在衬套上形成填充材料。填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

5. 发明申请

US20080303060A1 Semiconductor devices and methods of manufacturing thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080303060A1
公开(公告)日：2008-12-11
申请号：US11810633
申请日：2007-06-06
申请人： Jin-Ping Han , Henry Utomo , Jiang Yan , Alois Gutmann , Thomas W. Dyer
发明人： Jin-Ping Han , Henry Utomo , Jiang Yan , Alois Gutmann , Thomas W. Dyer
IPC分类号： H01L29/778 , H01L21/20 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a first material on the semiconductor wafer, and affecting the semiconductor wafer with a manufacturing process. The manufacturing process inadvertently causes a portion of the first material to be removed. The portion of the first material is replaced with a second material.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片上形成第一材料，并通过制造工艺影响半导体晶片。制造过程无意中导致第一材料的一部分被去除。第一材料的部分被第二材料代替。

6. 发明申请

US20110237039A1 Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions 有权
标题翻译：形成具有SiGe源极/漏极区域的P沟道场效应晶体管的方法
公开(公告)号：US20110237039A1
公开(公告)日：2011-09-29
申请号：US12729486
申请日：2010-03-23
申请人： Jong-Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
发明人： Jong-Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer is then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
摘要翻译：形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。然后在栅极电极上形成掩模层。选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

7. 发明授权

US08198194B2 Methods of forming p-channel field effect transistors having SiGe source/drain regions 有权
标题翻译：形成具有SiGe源极/漏极区域的p沟道场效应晶体管的方法
公开(公告)号：US08198194B2
公开(公告)日：2012-06-12
申请号：US12729486
申请日：2010-03-23
申请人： Jong Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
发明人： Jong Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
IPC分类号： H01L21/311
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
摘要翻译：形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。然后在栅电极上图案化掩模层。选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

8. 发明申请

US20130001660A1 PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 失效
公开(公告)号：US20130001660A1
公开(公告)日：2013-01-03
申请号：US13615955
申请日：2012-09-14
申请人： Thomas W. Dyer
发明人： Thomas W. Dyer
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L21/30608 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/7848
摘要： Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

9. 发明授权

US07989357B2 Method of patterning semiconductor structure and structure thereof 有权
标题翻译：图案化半导体结构及其结构的方法
公开(公告)号：US07989357B2
公开(公告)日：2011-08-02
申请号：US11950741
申请日：2007-12-05
申请人： Thomas W. Dyer , James J. Toomey
发明人： Thomas W. Dyer , James J. Toomey
IPC分类号： H01L23/48
CPC分类号： H01L21/8258 , H01L21/0337 , H01L21/28123 , H01L21/31144
摘要： Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
摘要翻译：公开了图案化半导体结构的方法。该方法涉及晶体蚀刻技术以增强作为硬掩模的图案化单晶层。在一个实施例中，该方法包括将单晶硅层结合到非结晶保护层; 图案化单晶层以形成硬掩模; 增强硬面膜的图案; 常规蚀刻保护层后剥去硬掩模; 并在其上形成栅极氧化物。通过结晶蚀刻来进行硬掩模的增强图案化，以取代在具有直边和锐角的限定区域的端部处的圆化和尺寸变窄的光学效应。使用增强型图案化硬掩模的结果包括在半导体结构的衬底上的复合材料层。复合材料层包括在层内由直边限定的离散块中的不同材料。

10. 发明授权

US07964910B2 Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure 有权
标题翻译：平面场效应晶体管结构具有倾斜的结晶刻蚀源极/漏极凹槽和形成晶体管结构的方法
公开(公告)号：US07964910B2
公开(公告)日：2011-06-21
申请号：US11873731
申请日：2007-10-17
申请人： Thomas W. Dyer
发明人： Thomas W. Dyer
IPC分类号： H01L29/66
CPC分类号： H01L29/6656 , H01L21/30608 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/7848
摘要： Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.
摘要翻译：公开了一种结合外延沉积的源/漏半导体膜的晶体管和用于形成晶体管的方法。晶体蚀刻用于在硅衬底中的沟道区和沟槽隔离区之间形成凹陷。每个凹部具有与沟道区相邻的第一轮廓和具有与沟槽隔离区相邻的第二轮廓的第一侧。晶体蚀刻确保第二轮廓成角度，使得所有暴露的凹部表面都包含硅。因此，可以通过外延沉积而不形成凹坑来填充凹部。可以使用附加的工艺步骤来确保凹部的第一侧形成有增强通道区域中的期望应力的不同轮廓。

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