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1. 发明授权

US07863646B2 Dual oxide stress liner 有权
标题翻译：双重氧化应力衬垫
公开(公告)号：US07863646B2
公开(公告)日：2011-01-04
申请号：US11956043
申请日：2007-12-13
申请人： Michael P. Belyansky , Xiangdong Chen , Thomas W. Dyer , Geng Wang , Haining S. Yang
发明人： Michael P. Belyansky , Xiangdong Chen , Thomas W. Dyer , Geng Wang , Haining S. Yang
IPC分类号： H01L31/111 , H01L21/00
CPC分类号： H01L21/823807 , H01L27/092 , H01L29/7843
摘要： A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.
摘要翻译：晶体管结构包括位于衬底的第一区域中的第一类型的晶体管（例如，P型）和位于衬底的第二区域中的第二类型的晶体管（例如N型）。第一类型的应力层（压缩共形氮化物）位于第一类型的晶体管上方，并且第二类型的应力层（压缩拉伸氮化物）位于第二类型晶体管之上。此外，另一种第一类型的应力层（压缩氧化物）位于第一类型的晶体管之上。此外，另一第二类型的应力层（压缩氧化物）位于第二类型晶体管的上方。

2. 发明申请

US20090152638A1 DUAL OXIDE STRESS LINER 有权
标题翻译：双氧化层压力衬管
公开(公告)号：US20090152638A1
公开(公告)日：2009-06-18
申请号：US11956043
申请日：2007-12-13
申请人： MICHAEL P. BELYANSKY , Xiangdong Chen , Thomas W. Dyer , Geng Wang , Haining S. Yang
发明人： MICHAEL P. BELYANSKY , Xiangdong Chen , Thomas W. Dyer , Geng Wang , Haining S. Yang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L27/092 , H01L29/7843
摘要： A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.
摘要翻译：晶体管结构包括位于衬底的第一区域中的第一类型的晶体管（例如，P型）和位于衬底的第二区域中的第二类型的晶体管（例如N型）。第一类型的应力层（压缩共形氮化物）位于第一类型的晶体管上方，并且第二类型的应力层（压缩拉伸氮化物）位于第二类型晶体管之上。此外，另一种第一类型的应力层（压缩氧化物）位于第一类型的晶体管之上。此外，另一第二类型的应力层（压缩氧化物）位于第二类型晶体管的上方。

3. 发明申请

US20090108356A1 INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES 失效
标题翻译：多金属门工作功能结构的整合方案
公开(公告)号：US20090108356A1
公开(公告)日：2009-04-30
申请号：US11924053
申请日：2007-10-25
申请人： Kangguo Cheng , Michael P. Chudzik , Rama Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
发明人： Kangguo Cheng , Michael P. Chudzik , Rama Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
摘要翻译：在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整氧化层。还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

4. 发明授权

US07732872B2 Integration scheme for multiple metal gate work function structures 失效
标题翻译：多金属门功能结构的集成方案
公开(公告)号：US07732872B2
公开(公告)日：2010-06-08
申请号：US11924053
申请日：2007-10-25
申请人： Kangguo Cheng , Michael P. Chudzik , Ramachandra Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
发明人： Kangguo Cheng , Michael P. Chudzik , Ramachandra Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/088
CPC分类号： H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
摘要翻译：在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整氧化层。还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

5. 发明申请

US20120196413A1 METHOD AND STRUCTURE TO IMPROVE BODY EFFECT AND JUNCTION CAPACITANCE 审中-公开
标题翻译：改善身体效能和结电容的方法和结构
公开(公告)号：US20120196413A1
公开(公告)日：2012-08-02
申请号：US13432544
申请日：2012-03-28
申请人： Xiangdong Chen , Geng Wang , Da Zhang
发明人： Xiangdong Chen , Geng Wang , Da Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/1083 , H01L29/665 , H01L29/66575 , H01L29/78
摘要： A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.
摘要翻译：一种方法和结构在衬底内注入第一种杂质以在衬底内邻近衬底的顶表面形成沟道区; 在通道区域上方的衬底的顶表面上形成栅极堆叠; 并且在所述衬底内注入第二类型杂质以在所述衬底内邻近所述顶表面形成源区和漏区。沟道区域位于源区和漏区之间。第二种杂质相对于第一种杂质具有相反的极性。所述方法和结构相对于沟道区域内的第一类型杂质的浓度注入更大浓度的第一类型杂质，以在衬底下方（相对于顶表面）在通道内形成主体掺杂区域地区; 并且在源极和漏极区域之下（相对于顶表面）下方的衬底内形成辅助体掺杂区域。

6. 发明申请

US20070051996A1 METHOD OF FORMING A MOSFET WITH DUAL WORK FUNCTION MATERIALS 有权
标题翻译：形成具有双功能功能材料的MOSFET的方法
公开(公告)号：US20070051996A1
公开(公告)日：2007-03-08
申请号：US11553072
申请日：2006-10-26
申请人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
发明人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L27/10864
摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
摘要翻译：在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。晶体管栅极被设计代替通道。用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。存储节点附近的栅极材料为n型掺杂多晶硅。位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

7. 发明申请

US20060258060A1 Gate controlled floating well vertical MOSFET 审中-公开
标题翻译：门控浮动阱垂直MOSFET
公开(公告)号：US20060258060A1
公开(公告)日：2006-11-16
申请号：US11487809
申请日：2006-07-17
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
IPC分类号： H01L21/339
CPC分类号： H01L27/10864 , H01L27/0214 , H01L27/10841
摘要： A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate over-drive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.
摘要翻译：用于DRAM单元的新型晶体管结构包括两个深沟槽，一个沟槽包括用于存储数据的垂直存储单元，第二沟槽包括用于控制p阱电压的垂直控制单元，其实际上将部分 p阱处于浮置状态，从而与垂直传输晶体管处于截止状态时相比降低阈值电压。这使得晶体管在通常施加到存储和控制单元的两个门的有效字线电压期间表现出增加的栅极过驱动和驱动电流。

8. 发明授权

US08372721B2 Work function engineering for eDRAM MOSFETs 有权
标题翻译： eDRAM MOSFET的工作功能工程
公开(公告)号：US08372721B2
公开(公告)日：2013-02-12
申请号：US13343850
申请日：2012-01-05
申请人： Xiangdong Chen , Herbert L. Ho , Geng Wang
发明人： Xiangdong Chen , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10894 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.
摘要翻译：嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly）高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

9. 发明授权

US08299545B2 Method and structure to improve body effect and junction capacitance 有权
标题翻译：提高身体效果和结电容的方法和结构
公开(公告)号：US08299545B2
公开(公告)日：2012-10-30
申请号：US12695565
申请日：2010-01-28
申请人： Xiangdong Chen , Geng Wang , Da Zhang
发明人： Xiangdong Chen , Geng Wang , Da Zhang
IPC分类号： H01L29/02
CPC分类号： H01L29/1083 , H01L29/665 , H01L29/66575 , H01L29/78
摘要： A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.
摘要翻译：一种方法和结构在衬底内注入第一种杂质以在衬底内邻近衬底的顶表面形成沟道区; 在通道区域上方的衬底的顶表面上形成栅极堆叠; 并且在所述衬底内注入第二类型杂质以在所述衬底内邻近所述顶表面形成源区和漏区。沟道区域位于源区和漏区之间。第二种杂质相对于第一种杂质具有相反的极性。所述方法和结构相对于沟道区域内的第一类型杂质的浓度注入更大浓度的第一类型杂质，以在衬底下方（相对于顶表面）在通道内形成主体掺杂区域地区; 并且在源极和漏极区域之下（相对于顶表面）下方的衬底内形成辅助体掺杂区域。

10. 发明授权

US08129797B2 Work function engineering for eDRAM MOSFETs 有权
标题翻译： eDRAM MOSFET的工作功能工程
公开(公告)号：US08129797B2
公开(公告)日：2012-03-06
申请号：US12141311
申请日：2008-06-18
申请人： Xiangdong Chen , Herbert L. Ho , Geng Wang
发明人： Xiangdong Chen , Herbert L. Ho , Geng Wang
IPC分类号： H01L27/088
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10894 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.
摘要翻译：嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly）高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

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