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1. 发明申请

US20080009139A1 Structure in a substrate for the manufacturing of a semiconductor device and process for manufacturing of a semiconductor device 审中-公开
标题翻译：用于制造半导体器件的衬底中的结构和用于制造半导体器件的工艺
公开(公告)号：US20080009139A1
公开(公告)日：2008-01-10
申请号：US11481419
申请日：2006-07-05
申请人： Thomas Hecht , Kristin Schupke , Kevin Bauer , Steffen Mueller , Henry Bernhardt
发明人： Thomas Hecht , Kristin Schupke , Kevin Bauer , Steffen Mueller , Henry Bernhardt
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31111 , B81B2203/033 , B81C1/00595 , B81C2201/0133 , B81C2201/0142 , H01L27/1087
摘要： A structure in a substrate for the manufacturing of a semiconductor device, wherein a first material and at least one second material are to be etched by at least one etching medium, wherein the at least one second material has a higher etch rate for the at least one etching medium relative to the first material. The at least one second material occupies a space which is at least at one side adjacent to the first material so that an additional etching access to the first material is prepared when at least one etching medium etches the first and the second material.
摘要翻译：用于制造半导体器件的衬底中的结构，其中第一材料和至少一个第二材料将被至少一个蚀刻介质蚀刻，其中所述至少一个第二材料对于至少一个蚀刻速率具有更高的蚀刻速率一个蚀刻介质相对于第一材料。至少一个第二材料占据至少在与第一材料相邻的一侧的空间，使得当至少一个蚀刻介质蚀刻第一和第二材料时，准备对第一材料的另外的蚀刻访问。

2. 发明申请

US20080280446A1 METHOD OF PRODUCING A MICROSCOPIC HOLE IN A LAYER AND INTEGRATED DEVICE WITH A MICROSCOPIC HOLE IN A LAYER 审中-公开
标题翻译：在层中生产微孔和在一层中具有微孔的集成装置的方法
公开(公告)号：US20080280446A1
公开(公告)日：2008-11-13
申请号：US11745800
申请日：2007-05-08
申请人： Steffen Mueller , Odo Wunnicke , Henry Bernhardt
发明人： Steffen Mueller , Odo Wunnicke , Henry Bernhardt
IPC分类号： H01L21/311 , H01L23/48
CPC分类号： H01L21/76804 , H01L21/02164 , H01L21/02178 , H01L21/31111 , H01L21/31144 , H01L21/31608 , H01L21/31616 , H01L21/76802 , H01L21/76816 , H01L21/76831 , H01L21/76832 , H01L28/91
摘要： A microscopic hole is produced in a dielectric layer having a dielectric first material, a first surface and a second surface. In one embodiment, the tapered through-hole is etched from the second surface of the layer to the first surface of the layer. The tapered hole provides a first cross section near the first surface of the dielectric layer and a second cross section near the second surface of dielectric layer. A cladding is deposited at the inner surface of the through-hole. The cladding includes a second material and provides a thickness decreasing from the second surface to the first surface.
摘要翻译：在具有电介质第一材料，第一表面和第二表面的电介质层中产生微孔。在一个实施例中，锥形通孔从层的第二表面蚀刻到层的第一表面。锥形孔在电介质层的第一表面附近提供第一横截面，在电介质层的第二表面附近提供第二横截面。包层沉积在通孔的内表面。包层包括第二材料并提供从第二表面到第一表面减小的厚度。

3. 发明申请

US20070155139A1 Method for fabricating an integrated circuit on a semiconductor substrate 有权
标题翻译：在半导体衬底上制造集成电路的方法
公开(公告)号：US20070155139A1
公开(公告)日：2007-07-05
申请号：US11319793
申请日：2005-12-29
申请人： Thomas Hecht , Henry Bernhardt , Christian Kapteyn
发明人： Thomas Hecht , Henry Bernhardt , Christian Kapteyn
IPC分类号： H01L21/20
CPC分类号： H01L29/4925 , H01L21/02488 , H01L21/02491 , H01L21/02502 , H01L21/02513 , H01L21/02532 , H01L21/02667 , H01L21/28044 , H01L21/823437 , H01L21/823828 , H01L27/0629 , H01L27/10861 , H01L27/10873 , H01L29/66181
摘要： Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.
摘要翻译：包括导电层和多晶硅层的集成电路器件，其中所述集成电路器件还包括中间反应力层。该中间反应层配置在多晶硅层与导电层之间，能够抑制多晶硅层的结晶化。此外，中间反应层在多晶硅结晶温度以下为非晶态。

4. 发明授权

US07297983B2 Method for fabricating an integrated circuit on a semiconductor substrate 有权
公开(公告)号：US07297983B2
公开(公告)日：2007-11-20
申请号：US11319793
申请日：2005-12-29
申请人： Thomas Hecht , Henry Bernhardt , Christian Kapteyn
发明人： Thomas Hecht , Henry Bernhardt , Christian Kapteyn
IPC分类号： H01L29/04
CPC分类号： H01L29/4925 , H01L21/02488 , H01L21/02491 , H01L21/02502 , H01L21/02513 , H01L21/02532 , H01L21/02667 , H01L21/28044 , H01L21/823437 , H01L21/823828 , H01L27/0629 , H01L27/10861 , H01L27/10873 , H01L29/66181
摘要： Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.

5. 发明申请

US20070210367A1 Storage capacitor and method for producing such a storage capacitor 审中-公开
标题翻译：存储电容器及其制造方法
公开(公告)号：US20070210367A1
公开(公告)日：2007-09-13
申请号：US11606381
申请日：2006-11-30
申请人： Henry Bernhardt , Thomas Hecht , Michael Stadtmueller , Christian Kapteyn , Uwe Schroder , Yeong-Kwan Kim , Andreas Spitzer
发明人： Henry Bernhardt , Thomas Hecht , Michael Stadtmueller , Christian Kapteyn , Uwe Schroder , Yeong-Kwan Kim , Andreas Spitzer
IPC分类号： H01L29/94
CPC分类号： H01L28/40 , H01L27/10861
摘要： A storage capacitor includes a first electrode layer, second electrode layer and a dielectric interlayer arranged between the first electrode layer and the second electrode layer. The dielectric interlayer contains a high-k dielectric and at least one silicon-containing component.
摘要翻译：存储电容器包括布置在第一电极层和第二电极层之间的第一电极层，第二电极层和介电中间层。电介质中间层包含高k电介质和至少一种含硅组分。

6. 发明申请

US20080316675A1 METHOD FOR PRODUCING A DIELECTRIC INTERLAYER AND STORAGE CAPACITOR WITH SUCH A DIELECTRIC INTERLAYER 有权
标题翻译：用于制造具有这种介电中间层的电介质层和存储电容器的方法
公开(公告)号：US20080316675A1
公开(公告)日：2008-12-25
申请号：US12198005
申请日：2008-08-25
申请人： Bernd Hintze , Henry Bernhardt , Frank Bernhardt
发明人： Bernd Hintze , Henry Bernhardt , Frank Bernhardt
IPC分类号： H01G4/06
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L29/945
摘要： A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.
摘要翻译：特别是用于存储电容器的电介质中间层由经受温度处理的层序列形成，其中层序列至少具有第一金属氧化物层和通过将金属氮化物层完全氧化成更高级而形成的第二金属氧化物层价。

7. 发明申请

US20070272965A1 Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer 失效
标题翻译：用这种介电中间层制造电介质中间层和储能电容器的方法
公开(公告)号：US20070272965A1
公开(公告)日：2007-11-29
申请号：US11438700
申请日：2006-05-23
申请人： Bernd Hintze , Henry Bernhardt , Frank Bernhardt
发明人： Bernd Hintze , Henry Bernhardt , Frank Bernhardt
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L29/945
摘要： A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.
摘要翻译：特别是用于存储电容器的电介质中间层由经受温度处理的层序列形成，其中层序列至少具有第一金属氧化物层和通过将金属氮化物层完全氧化成更高级而形成的第二金属氧化物层价。

8. 发明授权

US07547646B2 Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates 失效
标题翻译：沟槽电容器结构和用于在半导体衬底中施加用于沟槽蚀刻工艺的覆盖层和掩模的工艺
公开(公告)号：US07547646B2
公开(公告)日：2009-06-16
申请号：US10974797
申请日：2004-10-28
申请人： Henry Bernhardt , Michael Stadtmüller , Olaf Storbeck , Stefan Kainz
发明人： Henry Bernhardt , Michael Stadtmüller , Olaf Storbeck , Stefan Kainz
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L27/10861 , H01L21/3081 , H01L21/3144 , H01L21/3185 , H01L27/1087 , H01L29/66181
摘要： A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer. The thermal nitriding is advantageously incorporated into a preanneal step for expelling oxygen from the semiconductor substrate, so that the semiconductor substrate is protected from the etching action of the expelled oxygen by the stress relief layer which is formed, there is no need for an additional temporary etching protection layer for the semiconductor substrate and the overall processing is streamlined.
摘要翻译：单晶半导体衬底和沉积的氮化硅层或衬垫氮化物之间的应力消除层由热生产的氮化硅形成。由热产生的氮化硅制成的应力消除层代替例如与掩模层结合在该位置上通常的二氧化硅层或焊盘氧化物。在包括由沉积的氮化硅形成的保护层部分的掩模图案化之后，根据本发明为应力消除层提供的材料减少了对随后的工艺步骤施加的限制，例如湿蚀刻步骤，在半导体衬底或半导体衬底中的结构以及应力消除层上均起作用。热氮化有利地结合到用于从半导体衬底排出氧的预退火步骤中，使得半导体衬底被形成的应力消除层免受排出的氧的蚀刻作用，不需要额外的临时用于半导体衬底的蚀刻保护层和整体处理被简化。

9. 发明授权

US07880212B2 Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer 有权
标题翻译：用这种介电中间层制造电介质中间层和储能电容器的方法
公开(公告)号：US07880212B2
公开(公告)日：2011-02-01
申请号：US12198005
申请日：2008-08-25
申请人： Bernd Hintze , Henry Bernhardt , Frank Bernhardt
发明人： Bernd Hintze , Henry Bernhardt , Frank Bernhardt
IPC分类号： H01L27/108
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L29/945
摘要： A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.
摘要翻译：特别是用于存储电容器的电介质中间层由经受温度处理的层序列形成，其中层序列至少具有第一金属氧化物层和通过将金属氮化物层完全氧化成更高级而形成的第二金属氧化物层价。

10. 发明授权

US07416952B2 Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer 失效
标题翻译：用这种介电中间层制造电介质中间层和储能电容器的方法
公开(公告)号：US07416952B2
公开(公告)日：2008-08-26
申请号：US11438700
申请日：2006-05-23
申请人： Bernd Hintze , Henry Bernhardt , Frank Bernhardt
发明人： Bernd Hintze , Henry Bernhardt , Frank Bernhardt
IPC分类号： H01L27/108 , H01L21/20
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L29/945
摘要： A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.
摘要翻译：特别是用于存储电容器的电介质中间层由经受温度处理的层序列形成，其中层序列至少具有第一金属氧化物层和通过将金属氮化物层完全氧化成更高级而形成的第二金属氧化物层价。

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