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1. 发明申请

US20070285976A1 Intergrated circuit having a precharging circuit 有权
标题翻译：具有预充电电路的集成电路
公开(公告)号：US20070285976A1
公开(公告)日：2007-12-13
申请号：US11450605
申请日：2006-06-09
申请人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
发明人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0071 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A memory includes a phase change element having a first side and a second side and a first line coupled to the first side of the element. The memory includes an access device coupled to the second side of the element and a second line coupled to the access device for controlling the access device. The memory includes a circuit for precharging the first line to a first voltage and for applying a voltage pulse to the second line such that a current pulse is generated through the access device to the element to program the element to a selected one of more than two states. The voltage pulse has an amplitude based on the selected state.
摘要翻译：存储器包括具有第一侧和第二侧以及耦合到元件的第一侧的第一线的相变元件。存储器包括耦合到元件的第二侧的访问设备和耦合到访问设备的用于控制访问设备的第二行。存储器包括用于将第一线路预充电到第一电压并且用于将电压脉冲施加到第二线路的电路，使得通过该接入装置向该元件生成电流脉冲以将该元件编程为多于两个中的所选择的一个状态。电压脉冲具有基于选择状态的幅度。

2. 发明授权

US07564710B2 Circuit for programming a memory element 有权
标题翻译：用于编程存储元件的电路
公开(公告)号：US07564710B2
公开(公告)日：2009-07-21
申请号：US11742090
申请日：2007-04-30
申请人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
发明人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
IPC分类号： G11C11/00 , G11C11/56
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2213/79
摘要： An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.
摘要翻译：集成电路包括被配置为被编程为至少三个电阻状态中的任一个的存储器元件和电路。电路被配置为通过向存储元件施加脉冲将存储器元件编程为至少三个电阻状态中的所选择的一个。脉冲包括至少三个尾部中的一个，其中每个尾部对应于至少三个电阻状态中的一个。

3. 发明申请

US20080266932A1 CIRCUIT FOR PROGRAMMING A MEMORY ELEMENT 有权
标题翻译：编程记忆元件电路
公开(公告)号：US20080266932A1
公开(公告)日：2008-10-30
申请号：US11742090
申请日：2007-04-30
申请人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
发明人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2213/79
摘要： An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.
摘要翻译：集成电路包括被配置为被编程为至少三个电阻状态中的任一个的存储器元件和电路。电路被配置为通过向存储元件施加脉冲将存储器元件编程为至少三个电阻状态中的所选择的一个。脉冲包括至少三个尾部中的一个，其中每个尾部对应于至少三个电阻状态中的一个。

4. 发明授权

US07626858B2 Integrated circuit having a precharging circuit 有权
标题翻译：具有预充电电路的集成电路
公开(公告)号：US07626858B2
公开(公告)日：2009-12-01
申请号：US11450605
申请日：2006-06-09
申请人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
发明人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0071 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A memory includes a phase change element having a first side and a second side and a first line coupled to the first side of the element. The memory includes an access device coupled to the second side of the element and a second line coupled to the access device for controlling the access device. The memory includes a circuit for precharging the first line to a first voltage and for applying a voltage pulse to the second line such that a current pulse is generated through the access device to the element to program the element to a selected one of more than two states. The voltage pulse has an amplitude based on the selected state.
摘要翻译：存储器包括具有第一侧和第二侧以及耦合到元件的第一侧的第一线的相变元件。存储器包括耦合到元件的第二侧的访问设备和耦合到访问设备的用于控制访问设备的第二行。存储器包括用于将第一线路预充电到第一电压并且用于将电压脉冲施加到第二线路的电路，使得通过该接入装置向该元件生成电流脉冲以将该元件编程为多于两个中的所选择的一个状态。电压脉冲具有基于选择状态的幅度。

5. 发明授权

US09437266B2 Unipolar programmable metallization cell 有权
标题翻译：单极可编程金属化电池
公开(公告)号：US09437266B2
公开(公告)日：2016-09-06
申请号：US13675923
申请日：2012-11-13
申请人： Feng-Ming Lee , Yu-Yu Lin , Ming-Hsiu Lee
发明人： Feng-Ming Lee , Yu-Yu Lin , Ming-Hsiu Lee
IPC分类号： H01L45/00 , G11C11/00 , H01L27/24
CPC分类号： G11C11/00 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145
摘要： A programmable metallization device comprises a first electrode and a second electrode, and a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the dielectric layer to represent a data value using bias voltages having the same polarity, enabling the use of diode access devices. To form a conductive bridge, a bias is applied that is high enough to cause ions to penetrate the conductive ion-barrier layer into the dielectric layer, which then form filaments or bridges. To destruct the conductive bridge, a bias of the same polarity is applied that causes current to flow through the structure, while ion flow is blocked by the conductive ion-barrier layer. As a result of Joule heating, any bridge in the dielectric layer disintegrates.
摘要翻译：可编程金属化器件包括在第一和第二电极之间串联的第一电极和第二电极以及电介质层，导电离子阻挡层和离子供给层。在操作中，在电介质层中形成或破坏导电桥，以使用具有相同极性的偏置电压来表示数据值，从而能够使用二极管接入装置。为了形成导电桥，施加足够高的偏压，使得离子将导电离子阻挡层穿透到电介质层中，然后形成细丝或桥。为了破坏导电桥，施加相同极性的偏压，导致电流流过结构，同时离子流被导电离子阻挡层阻挡。作为焦耳加热的结果，介电层中的任何桥分解。

6. 发明授权

US08674459B2 Three-dimensional memory devices and methods of manufacturing and operating the same 有权
标题翻译：三维存储器件及其制造和操作方法
公开(公告)号：US08674459B2
公开(公告)日：2014-03-18
申请号：US13022588
申请日：2011-02-07
申请人： Ming-Hsiu Lee , Yen-Hao Shih
发明人： Ming-Hsiu Lee , Yen-Hao Shih
IPC分类号： H01L29/78
CPC分类号： G11C13/0023 , G11C13/00 , G11C13/0004 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/66833 , H01L29/792
摘要： The invention describes a semiconductor cell including a gate, a dielectric layer, a channel layer, a source region, a drain region and an oxide region. The dielectric layer is adjacent to the gate. The channel layer is adjacent to the dielectric layer and is formed above a source region, a drain region, and an oxide region.
摘要翻译：本发明描述了一种包括栅极，电介质层，沟道层，源极区，漏极区和氧化物区的半导体单元。电介质层与栅极相邻。沟道层与电介质层相邻并且形成在源极区，漏极区和氧化物区的上方。

7. 发明申请

US20140027706A1 SWITCHING DEVICE AND OPERATING METHOD FOR THE SAME AND MEMORY ARRAY 有权
标题翻译：切换设备及其操作方法和存储器阵列
公开(公告)号：US20140027706A1
公开(公告)日：2014-01-30
申请号：US13561558
申请日：2012-07-30
申请人： Wei-Chih Chien , Feng-Ming Lee , Ming-Hsiu Lee
发明人： Wei-Chih Chien , Feng-Ming Lee , Ming-Hsiu Lee
IPC分类号： H01L27/24 , H03K17/975
CPC分类号： G11C13/0002 , G11C13/003 , H01L27/2409 , H01L43/02 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
摘要： A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.
摘要翻译：提供了一种切换装置及其操作方法及其存储器阵列。开关装置包括第一固体电解质，第二固体电解质和开关层。开关层与第一固体电解质和第二固体电解质相邻。

8. 发明授权

US08537609B2 Memory device and method of operating the same 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US08537609B2
公开(公告)日：2013-09-17
申请号：US13161129
申请日：2011-06-15
申请人： Ming-Hsiu Lee , Chieh-Fang Chen
发明人： Ming-Hsiu Lee , Chieh-Fang Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C8/10 , G11C11/005 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0073
摘要： A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.
摘要翻译：提供存储器件。存储器件包括存储器阵列; 电连接到存储器阵列的第一电路，并使存储器阵列以第一模式工作; 以及电连接到存储器阵列的第二电路，并且使存储器阵列以第二模式工作。

9. 发明申请

US20130153846A1 THREE DIMENSIONAL MEMORY ARRAY ADJACENT TO TRENCH SIDEWALLS 有权
标题翻译：三维尺寸记忆阵列
公开(公告)号：US20130153846A1
公开(公告)日：2013-06-20
申请号：US13330525
申请日：2011-12-19
申请人： Wei-Chih CHIEN , Ming-Hsiu Lee , Shih-Hung Chen
发明人： Wei-Chih CHIEN , Ming-Hsiu Lee , Shih-Hung Chen
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1633
摘要： A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.
摘要翻译：一种自对准堆叠式存储单元阵列结构及其制造方法。存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。

10. 发明申请

US20130026516A1 LIGHT-EMITTING DIODE (LED) PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF 审中-公开
标题翻译：发光二极管（LED）包装结构及其包装方法
公开(公告)号：US20130026516A1
公开(公告)日：2013-01-31
申请号：US13223479
申请日：2011-09-01
申请人： Jih-Fu Wang , Chien-Ping Huang , Wen-Hao Lee , Hsien-Wen Chen , Ming-Hsiu Lee
发明人： Jih-Fu Wang , Chien-Ping Huang , Wen-Hao Lee , Hsien-Wen Chen , Ming-Hsiu Lee
IPC分类号： H01L33/60
CPC分类号： H01L33/486 , H01L33/62 , H01L2224/48091 , H01L2933/0033 , H01L2924/00014
摘要： A light-emitting diode (LED) package structure and a packaging method thereof are provided. The packaging method includes: forming first conductive layers on a silicon substrate, and forming a reflection cavity and electrode via holes from a top surface of the silicon substrate; forming a reflection layer on predetermined areas of a surface of the reflection cavity, and forming second conductive layers and metal layers on surfaces of the electrode via holes; and mounting a chip and forming an encapsulant, so as to fabricate the LED package structure. In the present invention, there is no need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield.
摘要翻译：提供一种发光二极管（LED）封装结构及其封装方法。封装方法包括：在硅衬底上形成第一导电层，并从硅衬底的顶表面形成反射腔和电极通孔; 在所述反射腔的表面的规定区域上形成反射层，在所述电极通孔的表面形成第二导电层和金属层; 并安装芯片并形成密封剂，以制造LED封装结构。在本发明中，不需要在电极通孔中进行用于连接硅基板的上下导电层的至少两个电镀工艺，并且导电层在电极通孔中的连接不良的问题可以是避免了，从而使制造工艺简化和时间有效，并且还提高了总产量。

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