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1. 发明申请

US20060036987A1 Methods for optimizing package and silicon co-design of integrated circuit 有权
公开(公告)号：US20060036987A1
公开(公告)日：2006-02-16
申请号：US10918933
申请日：2004-08-16
申请人： Anwar Ali , Stan Mihelcic , James Monthie
发明人： Anwar Ali , Stan Mihelcic , James Monthie
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.

2. 发明授权

US07117467B2 Methods for optimizing package and silicon co-design of integrated circuit 有权
标题翻译：优化集成电路封装和硅协同设计的方法
公开(公告)号：US07117467B2
公开(公告)日：2006-10-03
申请号：US10918933
申请日：2004-08-16
申请人： Anwar Ali , Stan Mihelcic , James G. Monthie
发明人： Anwar Ali , Stan Mihelcic , James G. Monthie
IPC分类号： G06F17/50 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/488
CPC分类号： G06F17/5068
摘要： The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.
摘要翻译：本发明涉及用于优化集成电路的封装和硅协同设计的方法。基于包括至少一个凸块图案模板的第一库创建用于集成电路的复合凸块图案。然后审查集成电路的PCB和晶片约束。基于包括至少一个部分封装模板的第二库生成集成电路的部分封装设计。开始用于所述集成电路的部分硅设计。然后完成集成电路的完整封装设计。集成电路的全硅设计完成。

3. 发明授权

US08151237B2 Disabling unused IO resources in platform-based integrated circuits 失效
标题翻译：在基于平台的集成电路中禁用未使用的IO资源
公开(公告)号：US08151237B2
公开(公告)日：2012-04-03
申请号：US12229446
申请日：2008-08-22
申请人： Anwar Ali , Julie Beatty , Kalyan Doddapaneni
发明人： Anwar Ali , Julie Beatty , Kalyan Doddapaneni
IPC分类号： G06F17/50 , G06F7/38 , H03K19/00 , H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： G01R31/31712 , G01R31/31704
摘要： The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.
摘要翻译：本发明涉及用于在基于平台的集成电路中禁用未使用的IO资源的方法。从供应商接收到一个切片。该片包括客户未使用的IO电路。 IO电路被禁止。例如，当IO电路需要连接到电源时，IO电路的主输入/输出引脚与IO电路的电源总线短路。当IO电路需要连接到接地源时，IO电路的主输入/输出引脚短接到IO电路的接地总线。当IO电路需要悬浮时，IO电路的主输入/输出引脚不连接到片的任何焊盘单元。接下来，IO电路从客户的逻辑设计网表中删除。 IO电路插入供应商的物理设计数据库。

4. 发明授权

US07554133B1 Pad current splitting 有权
标题翻译：垫电流分流
公开(公告)号：US07554133B1
公开(公告)日：2009-06-30
申请号：US12119575
申请日：2008-05-13
申请人： Anwar Ali , Nenad Miladinovic , Kalyan Doddapaneni
发明人： Anwar Ali , Nenad Miladinovic , Kalyan Doddapaneni
IPC分类号： H01L27/10 , H01L29/73 , H01L23/52
CPC分类号： H01L23/5286 , H01L24/05 , H01L24/06 , H01L2224/05554 , H01L2924/01014 , H01L2924/01023 , H01L2924/01032 , H01L2924/01033 , H01L2924/14
摘要： An integrated circuit with a monolithic semiconducting substrate formed in a chip, where the chip has a peripheral edge, a backside, and an opposing top on which circuitry is formed. A first ring of bonding pads is formed along at least a portion of the peripheral edge. At least one of the bonding pads is configured as a power pad, and at least one of the bonding pads is configured as a ground pad. An intermediate power bus is disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. An intermediate ground bus is also disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. A power pad wire forms an exclusive electrical connection between the power pad and the intermediate power bus. A ground pad wire forms an exclusive electrical connection between the ground pad and the intermediate ground bus. A power strap forms an electrical connection between the intermediate power bus and a power mesh. A ground strap forms an electrical connection between the intermediate ground bus and a ground mesh.
摘要翻译：一种具有形成在芯片中的单片半导体衬底的集成电路，其中芯片具有外围边缘，背面和形成有电路的相对顶部。沿周边边缘的至少一部分形成第一接合焊盘。至少一个接合焊盘被配置为电源焊盘，并且至少一个焊盘被配置为接地焊盘。中间电源总线设置在芯片上的第一环焊盘的内部，并且不形成与任何核心器件的直接电连接。中间接地母线也设置在芯片上的第一环焊盘的内部，并且不形成与任何核心器件的直接电连接。电源焊盘线在电源板和中间电源总线之间形成专用电气连接。接地焊盘线在接地焊盘和中间接地总线之间形成专用电气连接。电源带形成中间电源总线和电源网之间的电连接。接地线在中间接地母线和地面网之间形成电气连接。

5. 发明授权

US07107561B2 Method of sizing via arrays and interconnects to reduce routing congestion in flip chip integrated circuits 有权
公开(公告)号：US07107561B2
公开(公告)日：2006-09-12
申请号：US10914657
申请日：2004-08-09
申请人： Anwar Ali , Wei Huang
发明人： Anwar Ali , Wei Huang
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： H01L24/11 , H01L21/76816 , H01L21/76838 , H01L23/5226 , H01L2224/13099 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/30105 , H01L2924/30107 , H01L2224/0401
摘要： A method and computer program are disclosed for reducing routing congestion in an integrated circuit design that include steps of: (a) receiving as input a design for an integrated circuit die having an inner metal layer and a top metal layer wherein the design includes electrical constraints of each of a plurality of I/O circuits in the integrated circuit die; (b) selecting a number of vias for a via array to form an electrical connection between the inner metal layer and the top metal layer of the integrated circuit die that connects a solder bump formed on the top metal layer to a corresponding one of the plurality of I/O circuits wherein the number of vias is selected to satisfy the electrical constraints of the corresponding one of the plurality of I/O circuits; and (c) generating as output the number of vias determined for the via array.

6. 发明授权

US06798069B1 Integrated circuit having adaptable core and input/output regions with multi-layer pad trace conductors 有权
标题翻译：集成电路具有适应性强的核心和输入/输出区域，具有多层焊盘跟踪导体
公开(公告)号：US06798069B1
公开(公告)日：2004-09-28
申请号：US10402054
申请日：2003-03-28
申请人： Anwar Ali , Tauman T. Lau , Kalyan Doddapaneni
发明人： Anwar Ali , Tauman T. Lau , Kalyan Doddapaneni
IPC分类号： H01L2348
CPC分类号： H01L24/06 , H01L23/50 , H01L24/45 , H01L24/49 , H01L2224/05554 , H01L2224/451 , H01L2224/4943 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/14 , H01L2924/1433 , H01L2924/00015 , H01L2224/05599
摘要： An integrated circuit is provided which includes at a first, a second, or a third row of bonding pads. A plurality of trace conductors is provided to route the signal of each bonding pad to an I/O ring and/or a core. The trace conductors of different metal widths are configured on a separate and distinct metal layers such that routing may be done above or below the bonding pad rows and other trace conductors. A plurality of vias is provided to connect between the different metal layers. This allows multiple rows of bonding pads to be arranged on the perimeters of the core without having to compromise for small pitch distances or longer routing paths.
摘要翻译：提供一种集成电路，其包括在第一，第二或第三排接合焊盘处。提供了多个迹线导体以将每个焊盘的信号路由到I / O环和/或核。不同金属宽度的迹线导体配置在单独和不同的金属层上，使得可以在焊盘行和其它迹线导体的上方或下方进行布线。提供多个通孔以连接不同的金属层。这允许将多排接合焊盘布置在芯的周边上，而不必对小间距距离或较长路由路径造成损害。

7. 发明授权

US07569472B2 Method and apparatus of power ring positioning to minimize crosstalk 有权
标题翻译：电源环定位的方法和设备，以减少串扰
公开(公告)号：US07569472B2
公开(公告)日：2009-08-04
申请号：US11590961
申请日：2006-10-31
申请人： Anwar Ali , Tauman T Lau , Kalyan Doddapaneni
发明人： Anwar Ali , Tauman T Lau , Kalyan Doddapaneni
IPC分类号： H01L21/44
CPC分类号： H01L23/552 , H01L23/3128 , H01L23/49838 , H01L23/49861 , H01L23/50 , H01L23/585 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/16225 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/48233 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/4943 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.
摘要翻译：公开了一种用于最小化串扰的功率环定位的方法和/或装置。在一个实施例中，一种方法包括在功率环和管芯之间产生指状物阵列，在管芯的接合焊盘和指状物阵列的特定手指之间施加信号线，以及在相邻接合点之间施加屏蔽线焊盘和电源环，使得屏蔽线比信号线长，并且不耦合到手指阵列中的任何一个。屏蔽线可以放置在信号线的相邻信号线之间，以使相邻的信号线之间的串扰最小化。

8. 发明申请

US20080320432A1 Disabling unused IO resources in platform-based integrated circuits 失效
公开(公告)号：US20080320432A1
公开(公告)日：2008-12-25
申请号：US12229446
申请日：2008-08-22
申请人： Anwar Ali , Julie Beatty , Kalyan Doddapaneni
发明人： Anwar Ali , Julie Beatty , Kalyan Doddapaneni
IPC分类号： G06F17/50 , G01R31/02
CPC分类号： G01R31/31712 , G01R31/31704
摘要： The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.

9. 发明授权

US07328417B2 Cell-based method for creating slotted metal in semiconductor designs 有权
标题翻译：用于在半导体设计中创建开槽金属的基于单元的方法
公开(公告)号：US07328417B2
公开(公告)日：2008-02-05
申请号：US10732395
申请日：2003-12-09
申请人： Anwar Ali , Tauman T. Lau , Kalyan Doddapaneni
发明人： Anwar Ali , Tauman T. Lau , Kalyan Doddapaneni
IPC分类号： G06F9/45
CPC分类号： G06F17/5068 , H01L27/0203
摘要： A computer-implemented method for creating slotted metal structures in a semiconductor design is disclosed. Aspects of the present invention include providing a library of different types of pre-slotted building block elements. Thereafter, during chip design, a plurality of the elements are selected from the library and placed in the design in abutment to form a composite slotted metal structure.
摘要翻译：公开了一种用于在半导体设计中产生开槽金属结构的计算机实现的方法。本发明的方面包括提供不同类型的预开槽构件块元件的库。此后，在芯片设计期间，从库中选择多个元件并将其放置在邻接的设计中以形成复合开槽金属结构。

10. 发明授权

US07075179B1 System for implementing a configurable integrated circuit 有权
公开(公告)号：US07075179B1
公开(公告)日：2006-07-11
申请号：US11016014
申请日：2004-12-17
申请人： Anwar Ali , Julie L. Beatty , Kalyan Doddapaneni
发明人： Anwar Ali , Julie L. Beatty , Kalyan Doddapaneni
IPC分类号： H01L23/48 , H01L23/485 , H01L23/50 , H01L23/552
CPC分类号： H01L24/06 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/05554 , H01L2224/451 , H01L2224/48227 , H01L2224/48233 , H01L2224/49171 , H01L2224/4943 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01076 , H01L2924/14 , H01L2924/1433 , H01L2924/00 , H01L2924/00015 , H01L2224/05599
摘要： The present invention provides a system for implementing a configurable integrated circuit (IC). Aspects of the invention include an IC die; a plurality of input/outputs (I/Os) coupled to the IC die; and a plurality power planes coupled to the IC die for providing power to the plurality of I/Os at different voltages. The plurality of power planes are configured concentrically around the IC die so that any one or more of the I/Os at any location on the IC die can be individually configured to connect to any of the power planes. As a result, any number of I/Os available on the IC die can operate at a given voltage.

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